Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-09-05
2006-09-05
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C438S655000
Reexamination Certificate
active
07101776
ABSTRACT:
There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.
REFERENCES:
patent: 6362063 (2002-03-01), Maszara et al.
patent: 6518155 (2003-02-01), Chau et al.
Tavel, B., et al., “Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate (˜Ω/□) without metal CMP nor etching,”IEDM 2001, p. 825-828, Dec. 2001.
Lee Ho
Lee Seung-Hwan
Rhee Hwa-Sung
Yoo Jae-Yoon
Lindsay Jr. Walter L.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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