Method of fabricating low voltage coefficient capacitor

Details Method of fabricating low voltage coefficient capacitor Method of fabricating low voltage coefficient capacitor

1999-06-09

2001-04-17

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S532000

Reexamination Certificate

active

06218240

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a low voltage coefficient capacitor.
2. Description of the Related Art
As the integration of an integrated circuit (IC) is increased by implementing deep sub-micron processes, the dimensions of all devices composing the IC are reduced. With the help of the reduction in the dimension of the devices, the operation speed of the devices can be increased.
The operation speed of a device is not only determined by the layout of an internal circuit density of the device, but is also affected by the material used for fabricating the device. The material used for fabricating the device plays an important role in increasing operation speed of the device when the integration of elements in an integrated circuit (IC) increases to approach deep sub-micron processes. For example, as logic devices approach to a 0.18-&mgr;m process, copper conductive wires, instead of aluminum conductive wires, are used in a multi-level metallization process to increase the operation speed.
Furthermore, the distance between a capacitor and a transistor in a dynamic random access memory (DRAM) is reduced due to the improvement in the process technology. Therefore, transmission time (or operation time) between the capacitor and the transistor is decreased, that is, that the operation speed is increased.
Conventionally, a top electrode and a bottom electrode of a capacitor in a DRAM are made of polysilicon. Because the polysilicon has a higher voltage coefficient, the operation speed of the capacitor is limited. Therefore, the overall performance of a DRAM can barely keep up with the performance of any present main board or center process unit (CPU). As a result, the operation speed of DRAM becomes the bottleneck of a computer system.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a low voltage coefficient capacitor to improve the performance of the capacitor.
The invention provides a method for fabricating a low voltage coefficient capacitor. A substrate is provided, wherein the substrate has a first region for forming a capacitor and a second region for forming a gate. A gate dielectric layer is formed over the substrate, and then a polysilicon layer is formed on the gate dielectric layer. A first dielectric layer is formed on the polysilicon layer, after that the first dielectric layer in the first region is patterned. A doped polysilicon region is formed in the polysilicon layer in the first region. A silicide layer conformal to the substrate is then formed thereon, and a second dielectric layer is formed on the silicide layer. Next, a condutive layer is formed on the second dielectric layer. A capacitor structure is formed on the doped polysilicon region in the first region by patterning the conductive layer, the second dielectric layer and the silicide layer. Then, the first dielectric layer is removed. A gate structure is formed in the second region by patterning the polysilicon layer and the gate dielectric layer. A healing process is performed to recover defects in the exposed surfaces of the capacitor structure and the gate structure. Next, a lightly doped drain is formed in the second region. Spacers are formed on each sidewall of the capacitor structure, the gate structure and the doped polysilicon region, respectively. Then, a source/drain region is formed in the second region.
In the invention, a photomask is used for forming a doped polysilicon layer in a region predetermined to form a capacitor and a doped polysilicon layer in a region predetermined to form a gate. A silicide layer is formed on the doped polysilicon layer serving as a bottom electrode of a capacitor.
The invention is compatible with the existing process and is simple for a person skilled in the art to incorporate it into the existing process.
The invention provides a method for fabricating a low voltage coefficient capacitor to enhance the capacitor performance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5057447 (1991-10-01), Paterson
patent: 5108941 (1992-04-01), Paterson et al.
patent: 5130267 (1992-07-01), Kaya et al.
patent: 5393691 (1995-02-01), Hsu et al.
patent: 5683931 (1997-11-01), Takahashi
patent: 6033965 (2000-03-01), Lin et al.
patent: 6090656 (2000-07-01), Randazzo

Affiliated with

Also associated with

Rating

Method of fabricating low voltage coefficient capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating low voltage coefficient capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating low voltage coefficient capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2505609