Method of fabricating local interconnection using selective...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S598000, C438S607000, C438S674000

Reexamination Certificate

active

07049218

ABSTRACT:
In a method of fabricating local interconnection, a selective epitaxial growth seed layer pattern is formed on a region of a semiconductor substrate where a local interconnection is to be formed. A selective epitaxial layer is formed by performing epitaxial growth on the resultant structure. The resistance of the selective epitaxial layer is reduced to complete the local interconnection.

REFERENCES:
patent: 5118639 (1992-06-01), Roth et al.
patent: 5166771 (1992-11-01), Godinho et al.
patent: 5893741 (1999-04-01), Huang
patent: 6335250 (2002-01-01), Egi
patent: 2003/0011001 (2003-01-01), Chevalier et al.
patent: 2000114262 (2000-04-01), None
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Lattice Press, 2000, p. 245.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating local interconnection using selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating local interconnection using selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating local interconnection using selective... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3556975

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.