Method of fabricating interconnect lines and plate electrodes of

Details Method of fabricating interconnect lines and plate electrodes of Method of fabricating interconnect lines and plate electrodes of

1996-08-14

2000-07-18

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, H01L 218242

Patent

active

060906626

ABSTRACT:
A method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.

REFERENCES:
patent: 5079670 (1992-01-01), Tigelaar et al.
patent: 5604365 (1997-02-01), Kajigaya et al.

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