Method of fabricating gate of fin type transistor

Details Method of fabricating gate of fin type transistor Method of fabricating gate of fin type transistor

2006-07-28

2008-08-19

Nguyen, Ha (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S288000

Reexamination Certificate

active

07413943

ABSTRACT:
A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.

REFERENCES:
patent: 6835618 (2004-12-01), Dakshina-Murthy et al.
patent: 7-153944 (1995-06-01), None
patent: 11-68069 (1999-03-01), None
patent: 10-2005-0006836 (2005-01-01), None
English language abstract of Japanese Publication No. 7-153944.
English language abstract of Japanese Publication No. 11-68069.
English language abstract of Korean Publication No. 10-2005-0006836.

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