Method of fabricating flash memory cell

Details Method of fabricating flash memory cell Method of fabricating flash memory cell

2007-05-17

2009-02-17

Menz, Douglas M (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

07491607

ABSTRACT:
A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

REFERENCES:
patent: 5455792 (1995-10-01), Yi
patent: 5912488 (1999-06-01), Kim et al.
patent: 5991204 (1999-11-01), Chang
patent: 6091104 (2000-07-01), Chen
patent: 6584018 (2003-06-01), Tuan et al.

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