Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-08-09
2000-12-05
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438275, H01L 218242
Patent
active
061566055
ABSTRACT:
A DRAM device having a triple well structure and a manufacturing method of the device are disclosed. The DRAM device includes first and second well regions of a first conductivity type formed in a semiconductor substrate of the first conductivity type. The first and second well regions are spaced apart from each other. The DRAM device also includes a third well region of a second conductivity type formed in the semiconductor substrate to encapsulate one of the first and second well regions for electrically isolating the encapsulated region from the semiconductor substrate. At least one first MOS transistor and at least one memory cell are formed in one of the first and second well regions. At least one second MOS transistor is formed in the other of the first and second well regions. In the present invention, one of the first and second MOS transistors has a gate length less than the gate length of the other.
REFERENCES:
patent: 4417325 (1983-11-01), Harari
patent: 5045966 (1991-09-01), Alter
patent: 5320976 (1994-06-01), Chin et al.
patent: 5792682 (1998-08-01), McAdams et al.
Chaudhari Chandra
Samsung Electronics Co,. Ltd.
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