Method of fabricating concave capacitor including adhesion...

Details Method of fabricating concave capacitor including adhesion... Method of fabricating concave capacitor including adhesion...

1999-09-09

2001-09-04

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C438S644000

Reexamination Certificate

active

06284589

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating a capacitor of a semiconductor memory device.
2. Description of the Related Art
With an increase in the integration of dynamic random access memories (hereinafter abbreviated as DRAM), methods have been proposed, of thinning a dielectric film of a capacitor to increase capacitance in a restricted cell area, or of changing the structure of a capacitor lower electrode to a three-dimensional structure to increase the effective area of a capacitor.
However, even though the above-proposed methods are adopted, it is difficult to obtain a capacitance necessary for device operation in a memory device of 1 G DRAM or more from an existing dielectric. In order to solve the above problem, research has been actively conducted into substituting the dielectric film of a capacitor with a thin film formed of a material having high permittivity, such as,
Ta
2
O
5
, (Ba,Sr)TiO
3
(BST), PbZrTiO
3
(PZT), (Pb,La)(Zr,Ti)O
3
(PLZT), among others.
In the capacitor using the above-described high dielectric film, metals of the platinum group or oxides thereof, e.g., Pt, Ir, Ru, RuO
2
, IrO
2
, etc., instead of polysilicon are used as an electrode material.
Meanwhile, in a stacked-type capacitor having a three-dimensional structure, the lower electrode becomes higher and the interval between electrodes becomes narrower as the DRAM becomes more highly integrated. Due to limits in the platinum film etch technology, difficulties in separating storage nodes have appeared.
In order to solve this particular problem, a capacitor fabrication method by which difficulties in etching a platinum film can be avoided while using the above high dielectric film has been developed in many fields. For example, a concave capacitor has been proposed by Y. Kohyama et al., Symposium on VLSI Technology Digest of Technical Papers, p. 17, 1997.
According to a method of fabricating the proposed concave capacitor, an interlayer dielectric film is formed on a semiconductor substrate, a storage node hole is formed in the interlayer dielectric film, and ruthenium (Ru) is deposited to a predetermined thickness in the storage node hole, thereby forming a storage electrode.
When the concave capacitor is formed as described above, difficulties in the platinum-group metal etch process can be avoided, and the height of the storage node can be arbitrarily controlled as well. However, when forming the storage node of the concave capacitor, the sidewall of the interlayer dielectric film exposed by the storage node hole is weakly coupled to the storage node, which causes a phenomenon in which the storage node is lifted from the interlayer dielectric film upon subsequent deposition or thermal treatment. When this lifting phenomenon occurs, stress is applied to the entire structure of the capacitor. Thus, a bad influence can be exerted on the dielectric film of the capacitor and a plate electrode. In addition, electrical characteristics may be degraded, due to leakage current in a completely-fabricated capacitor.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method of fabricating a concave capacitor for semiconductor memory devices, by which a storage electrode is not lifted from an interlayer dielectric film.
Accordingly, to achieve the above object, in the concave capacitor fabricating method, an interlayer dielectric film is formed on a semiconductor substrate. A concave pattern having a storage node hole exposing part a portion of an upper surface of the semiconductor substrate is formed by patterning the interlayer dielectric film. An adhesion spacer is formed on a sidewall of the concave pattern exposed by the storage node hole. A lower electrode to cover the adhesion spacer and the upper surface of the semiconductor substrate exposed by the storage node hole is formed in the storage node hole itself.
The semiconductor substrate includes a contact having one end connected to the active region of the semiconductor substrate and the other end exposed on the upper surface of the semiconductor substrate. Here, the other end of the contact is exposed by the storage node hole. Preferably, the other end of the contact is formed of a material selected from the group consisting of TiN, TiAIN, TiSiN, TaN, TaSiN and TaAIN.
The interlayer dielectric film has a structure in which an etch stop layer, an oxide layer, and an anti-reflection layer are sequentially stacked. In one exemplary embodiment, the etch stop layer is formed of SiN.
In order to form the adhesion spacer, first, an adhesion layer is formed to cover the semiconductor substrate exposed by the storage node hole, and the sidewall and upper surface of the concave pattern. Next, the adhesion layer is etched back so that the adhesion spacer can remain only on the sidewall of the concave pattern.
The adhesion layer is formed of at least one material selected from the group consisting of Ti, TiN, TiSiN, TiAIN, TiO
2
, Ta, Ta
2
O
5
, TaN, TaAIN, TaSiN, AI
2
O
3
, W, WN, Co, and CoSi.
The adhesion layer can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a metal-organic deposition (MOD) method, a sol-gel method, or an atomic layer deposition (ALD) method.
In order to form the lower electrode, first, a first conductive layer is formed to cover an upper surface of the contact and the adhesion spacer which are exposed in the storage node hole, and the upper surface of the concave pattern. A sacrificial layer having a thickness that can completely fill the storage node hole is formed on the first conductive layer. The first conductive layer is divided into a plurality of lower electrodes by removing parts of the first conductive layer and sacrificial layer on the concave pattern until the upper surface of the concave pattern is exposed. The residual part of the sacrificial layer is removed.
The first conductive layer is formed of a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, and an oxide having a perovskite structure. Preferably, the sacrificial layer is a photoresist layer or an oxide layer.
The parts of the first conductive layer and sacrificial layer are removed by an etch-back method or a chemical mechanical polishing (CMP) method.
When the sacrificial layer is a photoresist layer, the residual part of the sacrificial layer is removed by ashing. When the sacrificial layer is an oxide layer, the residual part of the sacrificial layer is wet-etched out, thereby removing the layer.
In the method of fabricating a concave capacitor according to the present invention, after the lower electrode is formed, a dielectric layer is formed on the lower electrode, and a second conductive layer for forming an upper electrode is then formed on the dielectric layer, thereby forming the concave capacitor.
The dielectric layer is formed of at least one material selected from the group consisting of Ta
2
O
5
, AI
2
O
3
, SiO
2
, SrTiO
3
, BaTiO
3
, (Ba,Sr)TiO
3
, PbTiO
3
, (Pb,Zr)TiO
3
, Pb(La,Zr)TiO
3
, Sr
2
Bi
2
NbO
9
, Sr
2
Bi
2
TaO
9
, LiNbO
3
, and Pb(Mg,Nb)O
3
.
The second conductive layer is formed of a material selected from the group consisting of a platinum-group metal, a platinum-group metal oxide, TiN, and an oxide having a perovskite structure.
According to the present invention, bonding between the lower electrode and the concave pattern is enhanced by the adhesion spacer formed on the sidewall of the concave pattern. Thus, it would be of no concern if the lower electrode were to be lifted from the concave pattern.


REFERENCES:
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6057231 (2000-05-01), Givens et al.
patent: 6093638 (1999-11-01), Cho et al.
Y. Kohyama et al., A Fully Printable, Self-aligned and PlanarizedStacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond, VLS Tech. Digest, p. 17, 1997.

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