Method of fabricating CMOS type semiconductor device having...

Details Method of fabricating CMOS type semiconductor device having... Method of fabricating CMOS type semiconductor device having...

2007-03-20

2007-03-20

Lee, Hsien-Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S201000

Reexamination Certificate

active

11225914

ABSTRACT:
According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well. P-type impurity ions are implanted into the N-type well, using the second ion implantation mask pattern as an ion implantation mask, to form second source and drain regions on both sides of the second gate electrode.

REFERENCES:
patent: 6114206 (2000-09-01), Yu
patent: 6166413 (2000-12-01), Ono
patent: 6468851 (2002-10-01), Ang et al.
patent: 6967379 (2005-11-01), Matsuo

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