Method of fabricating CMOS device with dual gate electrode

Details Method of fabricating CMOS device with dual gate electrode Method of fabricating CMOS device with dual gate electrode

2002-06-06

2003-08-12

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C438S287000, C438S300000, C438S304000, C438S981000

Reexamination Certificate

active

06605501

ABSTRACT:

The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating vertical transistors.
BACKGROUND OF THE INVENTION
One way to increase chip packing density is to make vertical transistors. However, vertical transistor fabrication elevates the complexity of the process steps and conditions. This complexity is magnified when vertical transistors are fabricated with different gate oxide thicknesses for higher levels of circuitry integration.
U.S. Pat. No. 6,150,679 to Faltermeier et al. describes a process for fabricating a uniform gate oxide of a vertical transistor using ion implantation.
U.S. Pat. No. 5,969,384 to Hong describes a method of fabricating a flash memory having separate data programming and erasing terminals.
U.S. Pat. No. 5,633,519 to Yamazaki et al. describes a non-volatile floating gate semiconductor device.
U.S. Pat. No. 6,143,636 to Forbes et al. describes a method of forming a high density flash EEPROM having increased nonvolatile storage capacity.
U.S. Pat. No. 5,757,038 to Tiwari et al. describes a dual gate field effect transistor (FET) with an ultra thin channel.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one ore more embodiments of the present invention to provide an improved method of fabricating vertical transistors having different gate oxide thicknesses.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of one or more embodiments of the present invention may be accomplished in the following manner. Specifically, a substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar. The thinner first preliminary gate oxide is removed from over the first pillar and the thicker second preliminary gate oxide is thinned from over the second pillar. First final gate oxide is formed over the first pillar and second final gate oxide is formed on the second pillar. The second final gate oxide including the thinned second preliminary gate oxide. The second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.


REFERENCES:
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patent: 5480838 (1996-01-01), Mitsui
patent: 5633519 (1997-05-01), Yamazaki et al.
patent: 5757038 (1998-05-01), Tiwari et al.
patent: 5872037 (1999-02-01), Iwamatsu et al.
patent: 5969384 (1999-10-01), Hong
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150670 (2000-11-01), Faltermeier et al.
patent: 2002/0098633 (2002-07-01), Budge et al.

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