Method of fabricating CMOS device with dual gate electrode

Details Method of fabricating CMOS device with dual gate electrode Method of fabricating CMOS device with dual gate electrode

2002-01-02

2002-10-22

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000

Reexamination Certificate

active

06468851

ABSTRACT:

The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating dual gate complimentary metal-oxide semiconductor (CMOS) devices.
BACKGROUND OF THE INVENTION
The conventional dual poly-gate CMOS process includes the following problems:
1) diffusion of the p
+
poly gate deposit dopant (boron) through very thin oxide; and
2) gate depletion effect due to insufficient dopant activation in a low thermal-budget process with the gate depletion resulting in drive current degradation.
In attempts to overcome these problems associated with dual poly-gate CMOS processes, various dual-metal gate CMOS processes having two different metal materials for n-MOSFET (n-channel metal-oxide semiconductor field effect transistor) and p-MOSFET (p-channel metal-oxide semiconductor field effect transistor) (to achieve different work functions), respectively, have been proposed in the past. However, in general the dual-metal gate CMOS processes are very complicated and require many masking levels.
For example, U.S. Pat. No. 6,159,782 to Xiang et al. describes a method for fabricating short channel field effect transistors (N-channel MOSFET and P-channel MOSFET) with dual gates and with a gate dielectric having a high dielectric constant.
U.S. Pat. No. 6,043,157 to Gardner et al. describes a dual replacement gate process.
U.S. Pat. No. 6,033,943 to Gardner describes a semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thicknesses.
U.S. Pat. No. 6,171,911 to Yu describes a method for forming dual gate oxides on integrated circuits with advanced logic devices.
U.S. Pat. No. 5,918,116 to Chittipeddi describes a process for forming gate oxides possessing different thicknesses on a semiconductor substrate.
U.S. Pat. No. 5,750,428 to Chang describes a self-aligned non-volatile process with differentially grown gate oxide thicknesses to fabricate an electrically erasable programmable read only memory (EEPROM).
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved method of fabricating a dual-gate CMOS device.
Another object of the present invention to provide an improved method of fabricating a dual-gate CMOS device having n+ poly/metal gate for an n-MOSFET and a metal gate for a p-MOSFET.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a wafer is provided having an N-MOSFET region and a P-MOSFET region. A sacrificial gate layer/doped N
+
poly-1 layer/gate insulator layer stack is formed over the wafer. The N-MOSFET sacrificial gate layer is patterned to form a once patterned sacrificial gate layer only within the N-MOSFET region, exposing the doped N
+
poly-1 layer within the P-MOSFET region. An undoped poly-2 layer is formed over the once patterned sacrificial gate layer and the exposed N
+
poly-1 layer within the P-MOSFET region. The undoped poly-2 layer is planarized to form a planarized undoped poly-2 layer only within the P-MOSFET region. The once patterned sacrificial gate layer, the doped N
+
poly-1 layer and the gate insulator layer within the N-MOSFET region are planarized to form an initial N-MOSFET gate electrode stack having exposed sidewalls. The planarized undoped poly-2 layer, the doped N
+
poly-1 layer and the gate insulator layer within the P-MOSFET region are planarized to form an initial P-MOSFET gate electrode stack having exposed sidewalls. Sidewall spacers are formed adjacent the exposed sidewalls of the initial N-MOSFET and P-MOSFET gate electrode stacks. An intermetal dielectric layer is formed adjacent and between the initial N-MOSFET and P-MOSFET gate electrode stacks. The initial P-MOSFET gate electrode stack is removed to form a P-MOSFET gate cavity exposing a portion of the wafer. A second P-MOSFET gate insulator layer is formed within the P-MOSFET gate cavity over the exposed portion of the wafer. The upper sacrificial gate layer of the initial N-MOSFET gate electrode stack is removed to form an N-MOSFET gate cavity. A metal layer is formed over the structure, filling the remaining P-MOSFET gate cavity and the N-MOSFET gate cavity. The metal layer is planarized to remove the excess metal from over the intermetal dielectric layer leaving planarized N-MOSFET metal gate electrode cap within N-MOSFET gate cavity to form a finalized N-MOSFET and planarized P-MOSFET metal gate within the remaining P-MOSFET gate cavity to form a finalized P-MOSFET, thus completing formation of the dual gate electrode CMOS device.


REFERENCES:
patent: 5750428 (1998-05-01), Chang
patent: 5918116 (1999-06-01), Chittipeddi
patent: 6033943 (2000-03-01), Gardner
patent: 6043157 (2000-03-01), Gardner et al.
patent: 6130123 (2000-10-01), Liang et al.
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6171911 (2001-01-01), Yu
patent: 6333244 (2001-12-01), Yu
patent: 6387743 (2002-05-01), Shiozawa et al.

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