Method of fabricating cell of flash memory device

Details Method of fabricating cell of flash memory device Method of fabricating cell of flash memory device

2001-07-12

2003-06-03

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000, C257S315000, C257S316000

Reexamination Certificate

active

06573139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating a cell of a flash memory device.
2. Description of the Related Art
In a semiconductor flash memory device, information stored in a memory cell is not lost even though power is not supplied to the flash memory device. Thus, the flash memory device is widely used in computer memory cards. A cell on which a floating gate electrode and a control gate electrode are stacked in order is widely employed as a unit cell of the flash memory device.
FIG. 1
is a layout view of parts of a cell array region of a conventional NOR-type flash memory device. A plurality of word line patterns
115
are arranged in parallel with one another, and an active region pattern
111
crosses the word line patterns
115
. Common source region patterns S extending from the active region pattern
111
are arranged in parallel with the word line patterns
115
between a pair of the word line patterns
115
. The active region pattern
111
facing the common source region patterns S between the word line patterns
115
corresponds to drain regions D of a cell. Bit line contact patterns
117
are arranged in each of the drain regions D, and bit line patterns
119
covering the bit line contact patterns
117
are arranged perpendicular to the word line patterns
115
. Etching mask patterns
113
for separating floating gates of cells neighboring the word line patterns
115
are arranged between the bit line patterns
119
.
In order to improve the characteristics of a unit cell of the flash memory device having the structure of
FIG. 1
, it is important to increase capacitance between the floating gate electrode and the control gate electrode. A technique in which an interval between neighboring floating gate electrodes is formed to be smaller than the resolution limit of a photolithographic process using the etching mask patterns
113
and a technique in which a spacer remains along edges of the floating gate electrodes for maximizing an area where the floating gate electrodes overlap with the control gate electrodes, are used as methods for increasing the capacitance.
One of the techniques is disclosed in U.S. Pat. No. 5,675,162. In U.S. Pat. No. 5,675,162, a spacer is formed on top of edges of the floating gate electrodes, and a dielectric layer composed of oxide-nitride-oxide (ONO) or nitride-oxide (NO) material and control gate electrodes are stacked on top of the floating gate electrodes, thus maximizing the capacitance between the floating gate electrodes and the control gate electrodes. However, since the upper portion of the spacer formed on the floating gate electrodes has a pointed shape, the electric field has a high flux between the spacer and the control gate electrode. Thus, a breakdown voltage across the dielectric layer interposed between the floating gate electrode and the control gate electrode is reduced, and the reliability of a dielectric layer and the device is reduced.
Another method for increasing the area overlapped by the floating gate electrode and the control gate electrode is described in
FIGS. 2 through 5
, which are sectional views taken along line B-B′ of FIG.
1
. In
FIG. 2
, a device isolation layer
12
defining an active region is formed on a semiconductor substrate
10
using an active region pattern
111
. A 50-100 Å thick thin tunnel oxide film
14
is formed on the active region. The tunnel oxide film
14
is formed of thermal oxide. A polysilicon layer
16
and an antireflective layer
18
are sequentially formed on the entire surface of the semiconductor substrate on which the tunnel oxide film
14
is formed. A photoresist etching mask pattern
20
is formed on a first upper portion of the antireflective layer
18
.
In
FIG. 3
, all of the antireflective layer
18
and parts of the polysilicon layer
16
are removed in areas not protected by the photoresist etching mask pattern
20
, so that an antireflective layer pattern
18
a
and polysilicon layers
16
and
16
a
having a recess are formed on the semiconductor substrate
10
. Next, after the photoresist etching mask pattern
20
is removed (not shown), a silicon nitride film
21
is formed over the antireflective layer pattern
18
a
and the polysilicon layers
16
and
16
a.
In
FIG. 4
, a spacer
22
formed of silicon nitride is formed along the sides of the antireflective layer pattern
18
a
and along the edges of both sides of the recess by etching back the entire surface of the silicon nitride film
21
. The polysilicon layers
16
and
16
a
are completely removed using the spacer
22
, thereby exposing the upper surface of the device isolation layer
12
.
In
FIG. 5
, the antireflective layer pattern
18
a
and the spacer
22
are removed using phosphoric acid. Next, the polysilicon layers
16
and
16
a
are converted into a doped polysilicon layer pattern
16
b
by doping them with impurity ions. An interlevel dielectric (ILD) layer
24
and a doped polysilicon layer
26
are sequentially formed on the entire surface of the semiconductor substrate on which the polysilicon layer pattern
16
b
including a step difference is formed. The ILD layer
24
is typically composed of oxide-nitride-oxide (ONO) or nitride-oxide (NO) material. Next, the doped polysilicon pattern
16
b
, the ILD layer
24
, and the doped polysilicon layer
26
are patterned using a predetermined photoresist mask pattern, and then, the floating gate electrode, the dielectric layer, and the control gate electrode are formed.
In these prior structures, the surface of the polysilicon layer
16
a
contacting the spacer
22
is damaged from etching during an etching process. Thus, a step difference is formed on the uppermost portion of the floating gate electrode and, similar to U.S. Pat. No. 5,675,162, the reliability of the ILD layer interposed between the floating gate electrode and the control gate electrode beneath a step difference deteriorates.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method of fabricating a cell of a flash memory device, in which an interval between neighboring floating gate electrodes can be reduced to less than a critical dimension (CD), and which includes a floating gate electrode in which etching damage and a step difference can be prevented.
According to the invention, there is provided a method of fabricating a cell of a flash memory device. A semiconductor substrate including a device isolation layer is provided. A first conductive layer is formed on the surface of the semiconductor substrate. A protective layer of a material having a high etching selectivity with respect to the device isolation layer and the first conductive layer is formed on the upper surface of the first conductive layer. Portions of the protective layer located directly above the device isolation layer are removed to form a protective layer pattern having a recess. The semiconductor substrate on which the protective layer pattern is formed is etched to expose the first conductive layer and to form a spacer of a material having a high etching selectivity with respect to the device isolation layer and the first conductive layer on lower edges of the recess. The exposed first conductive layer is patterned using the spacer to expose the surface of the device isolation layer. The spacer and the protective layer pattern are then removed.
The protective layer and the spacer may be formed of a silicon film containing nitrogen, for example, a silicon nitride film or a silicon oxynitride film. In a case where the spacer and the protective layer may be formed of the same material, the spacer and the protective layer can be removed using phosphoric acid at one time, thus simplifying the manufacturing process.
The first conductive layer may be a doped polysilicon layer in a NAND-type flash memory device, and may be an undoped polysilicon layer in a NOR-type flash memory device. If t

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