Method of fabricating bit lines

Details Method of fabricating bit lines Method of fabricating bit lines

1999-09-10

2001-10-16

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S626000, C438S633000, C438S634000, C438S636000, C438S637000, C438S672000, C438S692000, C438S697000

Reexamination Certificate

active

06303431

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88112072, filed Jul. 16, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a bit line.
2. Description of the Related Art
The cost of the integration circuit process is usually high. Reducing the use of masks can reduce the number of process steps, and thus makes fabrication of the integrated circuit more economical.
For example, the conventional process for fabricating bit line contacts and bit lines requires many steps. The first step is to form a dielectric layer over the substrate. Then, the dielectric layer is covered with a patterned photoresist layer that is applied to define the dielectric layer. An etching process is performed to form a bit line contact opening in the dielectric layer, using the photoresist layer as mask. The bit line contact opening is filled with a conducting layer to form a bit line contact. Next, the substrate is covered with another conducting layer that is applied to form a bit line. The other patterned photoresist layer is formed on the second conducting layer to define the second conducting layer. The second conducting layer is etched to form the bit line.
Since at least two masks are needed to fabricate bit line contacts and bit lines in the prior art integration circuit process, the process window is limited and the cost is burdensome.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating bit lines. A semiconductor substrate having isolation structures formed therein is provided. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain are formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A stop layer is formed on the semiconductor. A dielectric layer is formed over the stop layer. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. A conducting layer is formed to fill the bit line contact holes and the bit line trenches to form bit line contacts and patterned bit lines therein. The bit line contact holes and the bit line trenches are formed with the use of only one mask, so that the present invention can be used to reduce the number of process steps and the process cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5807779 (1998-09-01), Liaw
patent: 5885895 (1999-03-01), Liu et al.
patent: 5907781 (1999-05-01), Chen et al.
patent: 6025255 (2000-02-01), Chen et al.
patent: 6071802 (2000-06-01), Ban et al.

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