Method of fabricating an integrated circuit having devices arran

Details Method of fabricating an integrated circuit having devices arran Method of fabricating an integrated circuit having devices arran

1997-02-25

1999-06-29

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218234

Patent

active

059181265

ABSTRACT:
It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates. More specifically, in one embodiment the polysilicon masking reticle is increased in size in regions of high density polysilicon gates in comparison to regions of isolated polysilicon gates. In another embodiment, the reticle in regions of isolated polysilicon gates is sized normally but increased in size in regions of high density polysilicon gates. Following photomasking and etching, substantially identical polysilicon lengths are achieved in the isolated and dense gate regions.

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