Method of fabricating a semiconductor memory device

Details Method of fabricating a semiconductor memory device Method of fabricating a semiconductor memory device

2008-07-01

2008-07-01

Le, Thao X. (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C257S315000

Reexamination Certificate

active

07393748

ABSTRACT:
A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.

REFERENCES:
patent: 2006/0249773 (2006-11-01), Kai
patent: 2007/0138576 (2007-06-01), Mizukami et al.
patent: 7-94612 (1995-04-01), None
patent: 11-163303 (1999-06-01), None
patent: 2000-174241 (2000-06-01), None
U.S. Appl. No. 11/834,886, filed Aug. 7, 2007, Watanabe, et al.

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