Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-17
2007-04-17
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S734000, C438S738000, C438S692000, C257SE21008, C257S068000, C257S209000, C257S422000, C257SE29003, C257S129000
Reexamination Certificate
active
10874579
ABSTRACT:
A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.
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Cho Jung-Hun
Kwon Chul-Soon
Lee Don-Woo
Lee Yong-Sun
Moon Jung-Ho
Nhu David
Samsung Electronics Co,. Ltd.
Volentine & Whitt PLLC
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