Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-08
2001-02-06
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S254000
Reexamination Certificate
active
06184081
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a process used to fabricate a semiconductor device, and more specifically to a process used to fabricate a capacitor structure, for a random access memory, (DRAM), device.
(2) Description of the Prior Art
To achieve performance requirements for high density DRAM devices, stacked capacitor structures, featuring large surface areas, have been used. Stacked capacitor shapes, such as crown, or cylindrical shaped, structures, have allowed capacitance increases, resulting from increased capacitor surface area, to be realized, without increasing the lateral dimension of the capacitor, or without risking device reliability and yield, by decreasing the already thin, capacitor dielectric layer. However the use of crown, or cylindrical shaped, capacitor structures, arrived at by forming a crown shaped storage node, featuring large vertical shapes, can result in process difficulties when attempting to pattern the upper plate of the capacitor structure. The large vertical shapes, of the crown shaped storage node structure, present photolithographic patterning difficulties, in terms, of step height, critical image control, and mis-alignment.
This invention will describe a process for fabricating a DRAM, stacked capacitor structure, without the use of a specific photolithographic masking procedure, used with conventional processes, to create the capacitor upper plate structure, thus avoiding the difficulties in achieving critical dimension and correct alignment, in addition to the cost reduction realized via the reduction in a critical photolithographic masking step. The elimination of the upper plate, photolithographic procedure, is accomplished using a novel process sequence in the capacitor upper plate definition is achieved simultaneously with contact hole openings, made for bit line, capacitor, and substrate contact purposes, using one photolithographic mask, and using the same etching steps. The definition of the capacitor upper plate is made in an area in which the topography of a crown, or cylindrical shaped, storage node structure, is not present. The contact holes, opened in the polysilicon layer, used for the capacitor upper plate structure, are then lined with an insulator spacers, providing the necessary insulation between metal plug structures, in the contact holes, and the adjacent polysilicon upper plate structure. This process can be used for capacitor under bit line, (CUB), designs, as well as for capacitor over bit line, (COB), designs. Prior art, such as Yang et al, in U.S. Pat. No. 5,804,852, as well as Sun, in U.S. Pat. No. 5,648,291, show processes for creating capacitor under bit line structures, however these prior arts do not show the novel procedures, used in the present invention, such as the definition of the capacitor upper plate structure, during contact hole opening procedures.
SUMMARY OF THE INVENTION
It is an object of this invention to create a capacitor structure, for a DRAM device.
It is another object of this invention to define the capacitor upper plate structure, simultaneously with the opening of bit line, and substrate, contact hole openings, using the same photolithographic mask and dry etching procedures.
It is still another object of this invention to use insulator spacers on the sides of contact holes, to provide the needed insulation between metal plug structures, in the contact holes, and the adjacent capacitor upper plate structure.
In accordance with the present invention a method of fabricating a DRAM capacitor structure, featuring a capacitor upper plate structure, defined simultaneously with the creation of bit line, and substrate, contact hole openings, and featuring insulator spacers on the sides of the contact holes, is described. Polysilicon plug structures are formed in self-aligned contact openings, in an insulator layer, contacting source/drain regions, that are in turn located in a region of a semiconductor substrate, between polycide gate structures. Capacitor openings are next formed in a thick silicon oxide, thin silicon nitride, composite layer: with a first capacitor opening exposing the top surface of a polysilicon contact plug, used for capacitor contact purposes, and a second opening exposing an underlying insulator layer. Crown shaped, or cylindrical shaped, storage node structures are formed in the capacitor openings via deposition of the storage node conductive material, followed by removal of the storage node conductive material, from the top surface of the silicon oxide silicon nitride composite layer, resulting in the vertical features, of the storage node conductive material, on the sides of the capacitor openings, connected by a horizontal feature, of storage node conductive material, located at the bottom of the capacitor opening, contacting an underlying polysilicon plug, at the bottom of the first capacitor opening. After removal of the silicon oxide layer, of the composite insulator layer, a capacitor dielectric layer is formed, followed by the deposition of the polysilicon layer, to be used for the capacitor upper plate structure, with this polysilicon layer completely filling the narrow space between the two capacitor openings. The capacitor openings now contain a crown shaped storage node structure, located on the inside surfaces of the opening, and a polysilicon layer overlying the crown shaped storage node structure, with the capacitor dielectric layer located between these conductive layers.
After deposition of an insulator layer, contact holes are formed in a series of layers, including through the polysilicon layer, used for the capacitor upper plate structure. The same photolithographic mask, and dry etching procedures, used to create the contact holes, also allow definition, or isolation of a polysilicon shape, to be used as the capacitor upper plate shape. A first contact hole opening, exposes the top surface of a polysilicon plug, to be used for bit line contact, while a second contact opening, used for substrate contact, exposes a portion of the semiconductor substrate. A third contact opening, exposes a portion of the polysilicon layer, located in the space between filled, capacitor openings. The contact opening, and capacitor upper plate definition procedure also features an isotropic cycle used for the polysilicon layer, to intentionally create an undercut polysilicon region, in the contact holes. Silicon nitride spacers are next formed on the sides of all contact holes, including a thicker spacer, located in undercut polysilicon regions of the contact hole. Metal plug structures are formed in the contact holes, followed by the formation of overlying metal interconnect structures. The crown shaped, DRAM capacitor structure, now offers increased surface area as a result of an upper capacitor plate, defined during the contact hole opening procedure, now overlying two crown shaped storage node structures, each residing in a capacitor opening.
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Chen Bi-Ling
Ho Yu-Chun
Jeng Erik S.
Kuo Ming-Hong
Lin Wei-Ray
Ackerman Stephen B.
Saile George O.
Trinh Michael
Vanguard International Semiconductor Corporation
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