Method of fabricating a capacitor of a semiconductor device

Details Method of fabricating a capacitor of a semiconductor device Method of fabricating a capacitor of a semiconductor device

2003-04-04

2004-09-28

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000

Reexamination Certificate

active

06797561

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a capacitor of a semiconductor device having a dielectric layer consisting of a sequentially stacked aluminum oxide layer and a titanium oxide layer.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the planar area occupied by capacitors of the semiconductor devices decreases. As is well known in the art, the capacitance of a capacitor is proportional to the dielectric constant of the dielectric layer thereof and the area of the electrodes of the capacitor. Accordingly, reducing the area of a capacitor to accommodate high integration results in a reduction in the capacitance of the capacitor. In order to compensate for this reduction in capacitance, there is suggested a method in which a dielectric layer with a high dielectric constant is used as the dielectric layer of a capacitor.
FIG. 1
illustrates a sectional view of a cell capacitor of a general DRAM memory device.
Referring to
FIG. 1
, a lower electrode
40
of a circular pipe with a closed bottom surface is disposed on a predetermined region of a semiconductor substrate (not shown). An interlayer dielectric (ILD)
10
is disposed beneath the lower electrode
40
to cover the semiconductor substrate. In addition, a contact plug
20
is formed in the ILD
10
to be contacted with the bottom surface of the lower electrode
40
.
A support pattern
30
is disposed on the ILD
10
; the support pattern
30
has an upper surface lower than that of the lower electrode
40
and covers the outer wall of the lower portion of the lower electrode
40
. An upper electrode
60
is disposed on the support pattern
30
to pass over the lower electrode
40
.
A capacitor dielectric layer
50
is interposed between the upper electrode
60
and the lower electrode
40
. Here, the capacitor dielectric layer
50
covers the surface of the lower electrode
40
at a uniform thickness and may extend to the upper surface of the support pattern
30
.
Conventionally, the capacitor dielectric layer
50
is formed of at least one material selected from silicon oxide and silicon nitride. However, the dielectric constant of silicon oxide and silicon nitride is too low to overcome a reduction in capacitance caused by a conventional fabricating method as described above. To compensate for this reduction in capacitance, there is disclosed a technology in which an aluminum oxide layer and a titanium oxide layer having a high dielectric constant are used as the dielectric layer of a capacitor. However, if the aluminum oxide layer and the titanium oxide layer are used as a capacitor dielectric layer, the leakage current characteristic degenerates according to the temperature of a subsequent process.
FIG. 2
is a graph illustrating a relationship between a process temperature for forming an upper electrode of a capacitor and a leakage current characteristic of the capacitor for two capacitors having different upper electrodes.
Referring to
FIG. 2
, a sequentially stacked aluminum oxide layer and titanium oxide layer are used as the dielectric layer
50
of the capacitor described in FIG.
1
. Here, the aluminum oxide layer and the titanium oxide layer are formed to have thicknesses of 40 Å and 50 Å, respectively. In addition, the upper electrode
60
is formed of polycrystalline silicon in trace
1
and tungsten in trace
2
.
In the capacitor indicated by trace
2
, the upper electrode of tungsten is formed by chemical vapor deposition (CVD) at a process temperature of 500° C. On the other hand, in the capacitor indicated by trace
1
, the upper electrode of polycrystalline silicon is made by forming amorphous silicon by CVD and performing a thermal annealing to crystallize the amorphous silicon. Here, the thermal annealing is performed at 650° C.
When the upper electrode
60
is made of polycrystalline silicon, as illustrated by trace
1
, the leakage current of the capacitor is measured 0.1 pA/Cell or more when an applied voltage is 2 V. On the other hand, when the upper electrode
60
is made of tungsten, as illustrated by trace
2
, the leakage current of the capacitor is measured 0.1 fA/Cell or less under the same applied voltage. This difference between leakage currents is due to the difference in process temperatures at which the upper electrodes
60
are formed.
For convenience of a subsequent process, it is desirable that the upper electrode
60
be made of the polycrystalline silicon. It is generally well known that polycrystalline silicon is crystallized at 650° C. However, as described above, the thermal annealing temperature of 650° C. increases leakage current of the capacitor, which limits the use of polycrystalline silicon as the upper electrode
60
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a capacitor of a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the prior art.
A feature of an embodiment of the present invention is to provide a method of fabricating a capacitor of a semiconductor device in which leakage current is minimized.
To provide a feature of an embodiment of the present invention, a method of fabricating a capacitor of a semiconductor device is provided, including forming a lower electrode on a semiconductor substrate; forming an aluminum oxide layer on the lower electrode; forming a titanium oxide layer on the aluminum oxide layer; and forming an upper electrode crossing over the lower electrode on the titanium oxide layer, wherein the aluminum oxide layer is formed to have a thickness in a range of from about 35 Å to about 60 Å, the titanium oxide layer is formed to have a thickness in a range of from about 2 Å to about 50 Å, and the upper electrode is formed at a temperature in a range of from about 150° C. to about 630° C.
Preferably, an upper limit of the temperature range at which the upper electrode is formed is decreased as the thickness of the titanium oxide layer is increased.
Preferably, the aluminum oxide layer is formed by one of a chemical vapor deposition and an atomic layer deposition. The titanium oxide layer is preferably formed by one of a chemical vapor deposition and an atomic layer deposition. Here, the aluminum oxide layer is formed preferably to a thickness of at least 35 Å.
It is desirable that the upper electrode is formed of at least one material selected from the group consisting of titanium nitride, polycrystalline silicon, tungsten, aluminum and platinum group elements.
Preferably, forming the upper electrode includes sequentially forming an adhesive conductive layer and an upper conductive layer on the titanium oxide layer and sequentially patterning the upper conductive layer and the adhesive conductive layer. The adhesive conductive layer may be a crystalline conductive layer, preferably a titanium nitride layer. In addition, it is desirable that the upper conductive layer is formed of at least one material selected from the group consisting of polycrystalline silicon, tungsten, aluminum and platinum group elements.
Forming the upper conductive layer of polycrystalline silicon may include forming a silicon layer on the adhesive conductive layer by chemical vapor deposition and thermally annealing the silicon layer to crystallize the silicon layer at a temperature in a range of from about 550° C. to about 630° C. The adhesive conductive layer and the upper conductive layer are preferably formed by one process selected from the group consisting of an atomic layer deposition, a chemical vapor deposition and a physical vapor deposition.
In general, a heat treatment may be performed after forming the upper electrode. The heat treatment may be performed at a temperature in a range of from about 500° C. to about 630° C. The upper limit of the temperature range at which the heat treatment is pe

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