Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2001-12-10
2003-06-17
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
C438S706000, C438S710000
Reexamination Certificate
active
06579796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of etching platinum using a silicon carbide mask. The present invention also pertains to methods of forming various semiconductor structures useful in the preparation of DRAM and FeRAM cells.
2. Brief Description of the Background Art
Dynamic random access memory (DRAM) cells are the current generation of high density memory cells. Ferroelectric random access memory (FeRAM) cells have been introduced as a future generation of very high density memory cells, potentially at the giga bit level and beyond. There are two basic requirements for storage capacitors for use in high density memory cells: 1) long retention time; and 2) tolerance to a large number of data refresh operations without significant deterioration of the charge characteristics during the lifetime of the memory cells. For example, for non-volatile memory (NVM) applications, the desired data retention time is over 10 years; for DRAM applications, data refresh operations may be performed more than one million times over the lifetime of the storage capacitors.
Recently, noble metals, such as platinum, iridium, and ruthenium, have been evaluated as new materials for electrodes of storage capacitors. Noble metals are known to have several advantages over conventional metals such as aluminum, including: 1) forms chemically and physically stable interfaces with high dielectric constant materials, such as PZT; 2) forms good electrical contacts with other metals used for interconnection; and 3) stable under high temperature O
2
ambient processes.
Storage capacitors formed with noble metals as electrodes and high dielectric constant materials show excellent characteristics in terms of data retention time and allowable refresh operations. As a result, storage capacitors formed with high dielectric constant materials and noble metals are viable candidates for the future generation of storage capacitors.
The formation of a storage capacitor including platinum typically involves pattern etching of a previously deposited platinum layer. One of the problems encountered with pattern etching of platinum is the identification of a suitable mask material. A suitable mask material for etching platinum must meet the following requirements: 1) the mask material must be capable of being deposited and patterned using standard industry techniques; 2) to avoid mask erosion during platinum etching, the mask material should not be easily etched using the etch chemistry used to etch the platinum (i.e., there should be good selectivity for etching platinum relative to the mask material); 3) the mask material must not be eroded during the etch process, such that a vertical (i.e., 80°-90°) etch profile can be obtained; and 4) at the end of etching, the mask material must be easily removable without disturbing other material layers within the etch stack.
Silicon oxide is currently used as a hard mask material for etching platinum. Silicon oxide meets the first three of the four requirements listed above. However, silicon oxide is not easily removable without disturbing other material layers within the etch stack when the etch stack includes an exposed doped dielectric layer or semiconductor substrate.
A current method of forming a semiconductor structure for use in the production of a DRAM cell is illustrated in
FIGS. 2A-2E
.
FIG. 2A
shows a typical starting structure
200
for forming the semiconductor structure. The starting structure
200
includes, from top to bottom, a patterned silicon oxide mask layer
210
, a layer
208
of platinum, a layer
206
of titanium nitride, a layer
204
of titanium, a doped premetal dielectric (PMD) layer
202
, overlying a semiconductor substrate
201
. A tungsten plug
203
has been previously formed in doped PMD layer
202
. Referring to
FIG. 2B
, the platinum layer
208
is pattern etched using the silicon oxide layer
210
as a mask. However, due to the difficulty in removing the silicon oxide masking layer
210
without etching into the underlying doped PMD layer
202
, the silicon oxide layer
210
must be removed prior to etching the titanium nitride and titanium layers
206
,
204
. Following the removal of silicon oxide layer
210
(as shown in FIG.
2
C), the titanium nitride and titanium layers
206
,
204
are pattern etched, exposing an upper surface
205
of doped PMD layer
202
, as shown in FIG.
2
D. The overlying patterned platinum layer
208
is used as a mask for pattern etching the titanium nitride and titanium layers
206
,
204
. However, the exposed upper surface
209
of the platinum layer
208
can be damaged during pattern etching of the titanium and titanium nitride layers
206
,
204
, creating a rough surface
209
on the platinum
208
. The roughened platinum surface
209
can create problems during the subsequent deposition of a high dielectric constant material. Because deposition of the high dielectric constant material
212
is conformal, as shown in
FIG. 2E
, the surface
213
of the deposited high dielectric constant material
212
takes on the atypical morphology of the underlying platinum surface
209
. This can lead to increased current leakage in the final semiconductor device.
Therefore, it would be desirable to provide a mask material for use in the etching of platinum which can be easily removed without damaging either the platinum or an underlying doped substrate material, and which can protect the platinum surface during the etching of underlying material layers.
SUMMARY OF THE INVENTION
Applicants have discovered that silicon carbide can be used as a hard mask for etching platinum and can be easily removed without damaging either the platinum or an underlying doped substrate material. As such, the silicon carbide mask layer can remain in place and protect the platinum surface during etching of a number of different underlying material layers. Further, silicon carbide can be deposited and patterned using standard industry techniques. Applicants have also discovered a particular etch chemistry for etching platinum using a silicon carbide hard mask which selectively etches platinum relative to the silicon carbide mask, while providing a vertical (i.e., 80°-90°) platinum etch profile.
Accordingly, a method of pattern etching a platinum layer comprises the steps of: a) providing an etch stack including a patterned silicon carbide layer overlying a layer of platinum; and b) pattern etching the platinum layer using a plasma generated from a source gas comprising Cl
2
, BCl
3
, and a nonreactive, diluent gas.
Silicon carbide remaining after etching the platinum layer is subsequently removed by dry etching using a plasma which is selective to etching the silicon carbide relative to other exposed materials. The residual silicon carbide masking material may be removed in many instances using a plasma generated from a source gas consisting essentially of Cl
2
, with the substrate at a low bias power, such as self-bias or at a low bias voltage in the range of about 100 V or less.
The present disclosure further includes methods of forming semiconductor structures useful in DRAM and FeRAM cells. One such method comprises the steps of: a) providing an etch stack including, from top to bottom, a patterned silicon carbide layer, a layer of platinum, a diffusion barrier layer, a wetting layer, and a layer of a doped dielectric material, overlying a semiconductor substrate; b) pattern etching the platinum layer using a plasma generated from a source gas comprising Cl
2
, BCl
3
, and a nonreactive, diluent gas; c) pattern etching the diffusion barrier layer and wetting layer to expose an upper surface of the doped dielectric material layer; and d) removing the silicon carbide layer.
An alternative embodiment of applicants' method comprises the steps of: a) providing an etch stack including, from top to bottom, a patterned silicon carbide layer, a patterned layer which serves as a barrier to the passage of hydrogen, a layer of platinum, a layer of iridium oxide, a layer of irid
Autryve Luc Van
Hwang Jeng H.
Ying Chentsau
Applied Materials Inc.
Bach Joseph
Bean Kathi
Church Shirley L.
Geyer Scott B.
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