Method of etching a trench in a silicon-containing...

Details Method of etching a trench in a silicon-containing... Method of etching a trench in a silicon-containing...

2002-05-10

2004-02-03

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S696000, C438S700000, C438S714000, C438S723000, C216S079000, C216S080000

Reexamination Certificate

active

06686293

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of etching a trench in a silicon-containing material having a dielectric constant of about 4 or less. The present invention also pertains to a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.
2. Brief Description of the Background Art
As device sizes decrease below 0.25 &mgr;m, the RC delay of interconnects will be the major barrier limiting the performance of ultra-large scale integrated circuits. The major components of RC delay are the capacitance of the intermetal dielectric (IMD) and the resistance of the interconnect lines. Low dielectric constant (k) materials have been integrated with copper metallization in dual damascene structures to maximize device performance that would otherwise be degraded by capacitance between metal lines, particularly in logic devices. Since the capacitance of a device structure is determined by both the inter-level and intra-level capacitance at the interconnect, it is important to use appropriate low k materials as the IMD. To decrease device capacitance, various low k materials, such as fluorinate-silicate glass (FSG), spin-on organics, and CVD deposited or spin-on deposited organosilicate glass (OSG) have been investigated for IMD in place of traditional oxides that have dielectric constants greater than 4.
Various approaches to manufacture dual damascene devices have been studied. However, a number of challenges in the process fabrication sequence still limit the realization of mass production. Some of the most critical processes of dual damascene fabrication are the dielectric etch steps. Relatively high dielectric constant materials, such as silicon nitride (k≈7), are often deposited as etch stop layers at the via (bottom etch stop layer) and trench (intermediate etch stop layer) levels to help control the etching process.
FIGS. 2A-2G
illustrate a generalized prior art procedure for forming a vertical interconnect within a dual damascene structure, where the damascene structure includes both a bottom and an intermediate etch stop layer.
FIG. 2A
shows a starting structure
200
for forming such a dual damascene structure. Structure
200
includes the following layers, from top to bottom, a patterned photoresist layer
212
, a first IMD layer
210
, an intermediate silicon nitride etch stop layer
208
, a second IMD layer
206
, and a bottom silicon nitride etch stop layer
204
, overlying a copper interconnect layer
202
. Referring to
FIG. 2B
, in order to form the vertical interconnect, typically a contact via, first IMD layer
210
is pattern etched, stopping on intermediate etch stop layer
208
. In order to etch through intermediate etch stop layer
208
, the etch chemistry (and/or processing conditions) must be changed to be more selective toward etching silicon nitride relative to the IMD, in order to avoid lateral etching into the sidewalls of overlying IMD layer
210
.
FIG. 2C
shows structure
200
after etching of intermediate etch stop layer
208
, where such lateral etching has been avoided. In order to etch through second IMD layer
206
, the etch chemistry (and/or processing conditions) must be changed again to be more selective toward etching the IMD relative to silicon nitride. Referring to
FIG. 2D
, second IMD layer
206
is pattern etched, stopping on bottom silicon nitride etch stop layer
204
, and forming intermediary structure
214
. Referring to
FIGS. 2E and 2F
, patterned photoresist layer
212
is then removed, and a new photoresist layer
216
is deposited and patterned. Referring to
FIG. 2G
, a trench
215
is then pattern etched in first IMD layer
210
, stopping on silicon nitride intermediate etch stop layer
208
. Subsequently, as shown in
FIG. 2H
, a dry etch is carried out to remove bottom silicon nitride etch stop layer
204
, and create a vertical interconnect
218
between copper interconnect layer
202
and an overlying metal interconnect layer (not shown) which will fill trench
215
.
In addition to being cumbersome from a process integration standpoint, in terms of the large number of individual deposition and etching steps, the use of an intermediate etch stop layer in a dual damascene process can significantly increase the overall effective k value of the integrated film stack. Therefore, it would be desirable to provide a dual damascene process which does not involve the use of an intermediate etch stop layer.
FIGS. 3A-3E
illustrate a generalized process for forming a vertical interconnect within a damascene structure without the use of an intermediate etch stop layer.
FIG. 3A
shows a starting structure
300
for forming such a dual damascene structure. Structure
300
includes the following layers, from top to bottom, a patterned photoresist layer
308
, an IMD layer
306
, and a bottom silicon nitride etch stop layer
304
, overlying a copper interconnect layer
302
. Structure
300
includes only one IMD layer and only one etch stop layer, and therefore contains two fewer layers than the starting structure
200
shown in FIG.
2
A. Referring to
FIG. 3B
, IMD layer
306
is pattern etched to form a vertical opening
310
, typically a contact via, stopping on bottom etch stop layer
304
. Referring to
FIGS. 3C and 3D
, patterned photoresist layer
308
is then removed, and a new photoresist layer
312
is deposited and patterned. A trench
314
is then pattern etched in IMD layer
306
to a predetermined depth, using an etch chemistry such as C
4
F
6
/O
2
/Ar or C
4
F
8
/CO/O
2
/Ar.
The process illustrated in
FIGS. 3A-3E
has two distinct advantages over the process illustrated in FIGS.
2
A-
2
H:1) it involves fewer deposition and etching steps and is therefore more cost effective; and 2) the final structure does not include an intermediate etch stop layer, and therefore the overall effective k value of the integrated film stack is decreased. However, as shown in
FIG. 3E
, the absence of an intermediate etch stop layer during etching of trench
314
typically results in moderate to severe microtrenching, creating a convex etch front with sharp corners
316
which can lead to current leakage and, ultimately, device failure.
Therefore, it would be desirable to provide a dual damascene process that does not include an intermediate etch stop layer, but allows better control over critical dimensions and etch profile during the trench etch process.
SUMMARY OF THE INVENTION
We have discovered a particular plasma etch chemistry for etching a trench in a silicon-based low k dielectric material such as a fluorinate-silicate glass (FSG) or an organosilicate glass (OSG), in the absence of a trench etch stop layer. The method which employs the plasma etch chemistry is particularly advantageous when the aspect ratio of the trench is about 6:1 or less. A silicon-based dielectric material having a patterned layer of photoresist over its upper surface is exposed to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas, where the additive gas composition and the quantity of additive gas depends on the particular etchant gas and the silicon-based dielectric composition.
When faceting of the upper portion of the etched trench occurs during etching, it is helpful to use a carbon monoxide additive gas. When microloading is occurring, it is helpful to use a chemically inert additive gas which provides a good source of ions, such as argon or neon or krypton, for example. In some instances, the best results are obtained using a combination of carbon monoxide with an inert gas such as, but not limited to, argon.
When the silicon-based low k dielectric material is FSG or a similar material which contains fluorine and little to no carbon, and the etchant gas contains a high ratio of fluorine to carbon, as is the case with CF
4
or C
2
F
6
, so that the fluorine:carbon ratio in the etchant gas is about 3:1 or greater, it is helpful to use carbon monoxide (CO) as the additive gas. The volumetric flow ratio of

Affiliated with

Also associated with

Rating

Method of etching a trench in a silicon-containing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of etching a trench in a silicon-containing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of etching a trench in a silicon-containing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3303361