Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-09-10
2004-08-17
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S719000, C438S725000
Reexamination Certificate
active
06777340
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching a layer of semiconductor material that contains silicon for the era of sub-micron devices features.
(2) Description of the Prior Art
The continuing trend in the development of semiconductor devices is driven by the desire to improve device performance, which imposes the necessity of reducing device feature size. Feature size for sub-micron devices, such as line width for interconnect traces of channel lengths for gate electrodes for sub-micron devices, is in the range of 0.25 &mgr;m or less.
The methods that are applied for the creation of device features fundamentally makes use of layers of photoresist, which are patterned and developed such that the remaining photoresist mask exposes an underlying surface in a desired pattern. Methods of photolithography (or E-beam or X-ray lithography) are used to expose the surface of the layer of photoresist, thereby changing the molecular structure (solubility) of the photoresist in such a way that the exposed photoresist either remains in place or can be removed.
Increased and continuing miniaturization of semiconductor devices has placed increasingly stringent demands on the methods of exposure that are used to create these ever-smaller device features. To gain an optimum exposure of a layer of photoresist, it is required that the light of the exposure source, such as a source of UV light, is sharply focused (enabling the creating of patterns of very small size) combined with good focusing resolution (enabling the creating of closely spaced patterns) while an optimum depth of focus assures that the layer of photoresist is exposed over an equal depth over the surface of the layer of photoresist. In addition, scattering of light while or after this light strikes the target surface (the surface of the layer of photoresist) must be severely limited since such light diffusion affects the target layer (of photoresist) in an unpredictable manner and is counter to the requirement that the light beam is sharply focused. For the latter reason, light reflection must be eliminated or severely limited after the light strikes the surface of the layer of photoresist, including reflection of the incident light from underlying surfaces such as the surface of a layer of metal or of the substrate. One of the methods that has been employed to obtain improved results in creating ultra-small device features has improved the light source by selecting shorter wavelength light for this light source or by increasing the energy by which the light is radiated. This however leads to other problems such as the emitted light penetrating the target layer and further affecting underlying layers such as layers of insulation.
Another approach that has been followed by the industry is to address and correspondingly optimize the surface or surfaces on which the light that is generated by the exposure source impacts. For instance, the use of a layer of Anti Reflective Coating (ARC) has long been recognized and used to suppress reflection of incident light back through for instant a layer of photoresist, diluting both the required depth of focus and the focusing resolution.
One of the main impacts on the photolithographic process that is caused by reduced device feature size is that the thickness of the layer of photoresist that is used for the pattern generation must accordingly be reduced, this to meet requirements of depth of focus of the light in the layer of photoresist, since reflected light has a less detrimental effect in a thinner layers of photoresist. The invention addresses these concerns and provides a method of layer creation, forming part of creation patterns of sub-micron size that can be applied to the creation of high-speed, high performance semiconductor devices having sub-micron device features.
U.S. Pat. No. 6,156,629 (Tao et al.) and U.S. Pat. No. 6,200,907 (Wang et al.) show dual hard mask.
U.S. Pat. No. 6,200,907 (Wang et al.), U.S. Pat. No. 6,171,763 (Wang et al.), and U.S. Pat. No. 5,886,410 (Chiang et al.) show other dual hard masks.
U.S. Pat. No. 6,069,091 (Chang et al.), U.S. Pat. No. 6,030,541 (Adkisson), U.S. Pat. No. 5,933,759 (Nguyen et al.) are related patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method of creating a pattern for semiconductor devices having ultra-small devices feature size.
It is another objective of the invention to prevent tilting of a layer of ultra-thin photoresist after this layer of photoresist has been patterned and developed.
It is another objective of the invention to provide a method of patterning and etching silicon based layers of material wherein device features with a size of 0.07 &mgr;m or less are to be created.
In accordance with the objectives of the invention a new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment of the invention, a hard mask layer is deposited over the surface of the silicon-based layer, a coating of organic ARC is deposited over the surface of the hard mask layer. The layers of organic ARC and the hard mask layer are patterned and etched in accordance with a pattern of openings that needs to be created in the layer of silicon based material. The patterned layer of ARC is removed after which the layer of silicon based material is etched in accordance with the pattern created in the layer of hard mask material. Under a second embodiment of the invention, a first and a second layer of hard mask material are deposited over the surface of a silicon based layer, a layer of ARC is applied over the surface of the second layer of hard mask material. The layers of ARC and the second hard mask material are patterned and etched in accordance with a pattern of openings that is to be created in the silicon based layer. The patterned layer of ARC is removed after which the patterned second layer of hard mask material is used to etch the first layer of hard mask material. The patterned and etched second and first layers of hard mask material are then used to etch the silicon-based material.
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Chen Fang-Chang
Chen Jeng-Horng
Chiu Hsien-Kuang
Chiu Yuan-Hung
Tao Hun-Jan
Ackerman Stephen B.
Chen Kin-Chan
Saile George O.
Taiwan Semiconductor Manufacturing Company
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