Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-12
2001-07-24
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S381000, C438S398000, C438S964000
Reexamination Certificate
active
06265264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a capacitor of a DRAM of a semiconductor device using hemispherical grains (HSG).
2. Description of the Related Art
As semiconductor devices become more highly integrated, the chips of such devices have become smaller. At the same time, a great effort has been made to increase the memory capacity of a small chip by increasing the capacitance of a capacitor of the chip without increasing the area occupied on the chip by the capacitor. Accordingly, an HSG forming process is presently used in the fabricating of semiconductor devices to maximize the surface area of a capacitor of a DRAM device.
However, the HSG process is problematic in that the HSG layer must be made by seeding undoped silicon, whereupon the depletion capacitance of the capacitor is reduced due to the low density of a bottom electrode and the total capacitance of the DRAM device is thereby reduced.
In order to solve this problem, recently, a method of fabricating a high density bottom electrode has been developed.
FIG. 1
illustrates such a method as applied to the fabricating of a conventional DRAM capacitor, and
FIG. 2
illustrates the structure of a bottom electrode of a DRAM capacitor fabricated according to the procedure illustrated in FIG.
1
. With reference to the drawings, the conventional method essentially involves the following six steps.
In the first step
10
, an inter-level insulating layer
102
is formed on a semiconductor substrate
100
.
In the second step
20
, a mask is used to facilitate an etching of the inter-level insulating layer
102
to expose a predetermined portion of the surface of the semiconductor substrate
100
, thereby forming a buried contact hole (h) in the inter-level insulating layer
102
.
In the third step
30
, an amorphous polysilicon layer is formed over the exposed surface of the substrate
100
, thereby filling the contact hole (h) and covering the inter-level insulating layer
102
. The amorphous silicon layer is doped with a high density of a p-type impurity which allows the material to serve as an electrode material. Specifically, the doping density of the p-type impurity is approximately 5×10
20
~6×10
20
atoms/cm
3
. Then, a mask is used to facilitate a selective etching of the polysilicon layer. As a result, a polysilicon bottom electrode is formed at a predetermined portion of the inter-level insulating layer
102
including within the contact hole (h).
In the fourth step
40
, HSG
106
is grown only at the exposed surface of the bottom electrode
104
in order to increase the effective surface area of the capacitor.
In the fifth step
50
, a cleaning process is performed for eliminating all of the particles (or contaminants) remaining on the resultant structure.
In the sixth step
60
, in order to enhance the surface density, PH
3
is doped into the HSG
106
under a “high temperature/low pressure” operational condition for 180 minutes. Such a condition refers to a high temperature of over 700° C., and a low pressure of 2~3 Torr. This step completes the formation of the bottom electrode.
However, if a bottom electrode of a DRAM capacitor is formed using the above-described fabricating method, the following problems occur.
Under the “high temperature/low pressure” condition established in the process of doping PH
3
into the HSG, the grains will compact and the HSG will deform into a shape in which the top thereof is rather broad.
FIG. 3
illustrates the HSG so deformed at the portion of the bottom electrode indicated as part I in FIG.
2
. In
FIG. 3
, reference symbols (a) and (b) respectively indicate shapes of the HSG before and after the PH
3
doping process.
If the HSG is deformed in this way in the process of doping the HSG with PH
3
, the p-type ions are not completely immersed. Some of the impurity ions exhibits out-gassing and are bounced off of the HSG, or even p-type ions that were successfully introduced in the bottom electrode
104
material become so heated that they are excited out of the HSG. Therefore, the doping density of the HSG can not be increased to a maximum extent.
While a DRAM comprising a capacitor having a bottom electrode fabricated in this way is operated, the breakdown voltage continuously increases, but the capacitance decreases due to the aforementioned problem. There is thus an urgent demand for solving this problem.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method of fabricating a capacitor of a DRAM device, which maximizes the capacitance characteristic of the DRAM device.
To achieve this object, the present invention provides a method of fabricating a bottom electrode of a capacitor of a semiconductor device, in which HSG at the surface of the electrode is doped with PH
3
under a “low temperature/high pressure” process condition to thereby prevent the HSG from changing shape and thereby maximize the dopant density of the HSG which, in turn, improves the capacitance and breakdown voltage characteristics of a DRAM device incorporating the capacitor.
The HSG is grown on a polysilicon layer doped with a p-type impurity preferably at a doping density of approximately 0.9×10
20
~1.1×10
20
atoms/cm
3
. The low temperature refers to a temperature below 700° C., and the high pressure refers to a pressure greater than 10 Torr. The PH
3
doping process is preferably performed within a short period of time, i.e., under 60 minutes.
REFERENCES:
patent: 5989973 (1999-11-01), Zahurak et al.
patent: 6069053 (2000-05-01), Ping et al.
patent: 6143605 (2000-11-01), Lou
patent: 553791-A1 (1993-08-01), None
patent: 80142-A1 (1997-10-01), None
patent: 874393 (1998-10-01), None
An Joong-il
Hyun Kyung-Ho
Koo Byung-Su
Kwak Sun-woo
Dang Trung
Jones Volentine PLLC
Samsung Electronics Co,. Ltd.
LandOfFree
Method of doping and HSG surface of a capacitor electrode... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of doping and HSG surface of a capacitor electrode..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of doping and HSG surface of a capacitor electrode... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2467706