Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-05
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S758000
Reexamination Certificate
active
06391776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method for depositing a copper seed layer having improved step coverage over a feature surface, and to the improved feature structure which is obtained using the method.
2. Brief Description of the Background Art
Due to the difficulty in etching a copper film to provide a desired semiconductor interconnect pattern, one of the preferred methods of providing copper interconnects is the damascene process, which requires the filling of embedded trenches and/or vias.
A typical damascene process for producing a multilevel structure having feature sizes in the range of 0.5 micron (&mgr;) or less would include: blanket deposition of a dielectric material over a semiconductor surface; patterning of the dielectric material to form openings; deposition of a conductive material over the surface of the dielectric material in sufficient amount to fill the openings; and removal of excessive conductive material from the substrate surface using a chemical reactant-based process, mechanical method, or combined chemical-mechanical polishing techniques. Due to problems with copper diffusion into underlying structures, a barrier layer is frequently used between the dielectric material and the copper fill material. In addition, to improve the adhesion of the copper fill to the barrier layer, a seed layer of copper is deposited over the barrier layer prior to deposition of the bulk copper fill material.
A major problem encountered during the copper fill of a feature is the entrapment of void spaces within the copper fill. For example, during copper fill of a feature such as a trench or via using chemical vapor deposition (CVD) there is a tendency to create voids within the filled opening; this is particularly true with regard to high aspect ratio features. Other disadvantages of a CVD process are the contaminants from the CVD reactant deposition source which may be found in the deposited conductive material and the costs associated with use of this technology. Filling of the copper feature with evaporated or sputtered copper is a cleaner process; however, the tendency to form voids still exists. Further, evaporative deposition is a relatively slow process, decreasing production rates. Sputtered copper may be used to provide copper fill, if used in combination with a reflow of the copper. However, the reflow process is typically also a time consuming process.
A typical sputtering technique for filling of high aspect ratio features of less than about 0.5 &mgr;m includes cold (typically below about 150° C.) deposition of sputtered copper over the feature surface, followed by an annealing process (without deposition) at temperatures in excess of about 400° C., to reflow the copper and obtain filling of the trench or via. However, such a reflow process presently is limited to aspect ratios of about 2:1 or less and typically requires more than a half hour of processing time.
U.S. Pat. No. 5,246,885 to Braren et al., issued Sep. 21, 1993, describes the problems listed above, and proposes the use of a laser ablation system for the filling of high aspect ratio features. Alloys, graded layers, and pure metals are deposited by ablating targets comprising more than one material using a beam of energy to strike the target at a particular angle. The ablated material is said to create a plasma composed primarily of ions of the ablated material, where the plasma is translated with high directionality toward a surface on which the material is to be deposited.
U.S. Pat. No. 5,312,509 of Rudolph Eschbach, issued May 17, 1974, discloses a manufacturing system for low temperature chemical vapor deposition of high purity metals. In particular, a semiconductor substrate including etched patterns is plasma cleaned; subsequently, the substrate is coated with adhesion and nucleation seed layers. A reactor connected to the process chamber containing the substrate sublimes a precursor of the metal to be deposited, which is then transported to the substrate. The heated chuck on which the substrate sits heats the substrate above the dissociation temperature of the precursor, releasing the metal from the precursor onto the substrate to nucleate the metal species onto the seed layer on the substrate. Although an adhesion barrier layer and a seed layer (if required) are said to be deposited using sputter deposition, the copper layer is applied solely by CVD deposition, to avoid the sidewall voiding which is said to occur if sputtering is used for the copper deposition.
U.S. Pat. No. 5,354,712 to Ho et al., issued Oct. 11, 1994, describes a method for forming interconnect structures for integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the side-walls and bottom of interconnect trenches defined in a dielectric layer. Subsequently, a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench.
Despite all of the above-described development efforts, there remained a need for a method of producing copper interconnect features which did not require the use of particularly complex equipment; which provided good step coverage for small, high aspect ratio features; which could be carried out at temperatures below about 450° C.; and, which produced an interconnect structure which is essentially void-free.
Very recently, copper filled semiconductor features were produced using electroplating techniques employing particularly clean plating solutions. This method for depositing copper works well when a continuous, conformal copper seed layer is in place on the surface of the feature at the time of initiation of electroplating. However, if there are any discontinuities in the copper seed layer, voids are created within the copper fill where there are discontinuities in the seed layer. This makes it critically important to have a continuous copper seed layer over the entire feature surface. When the feature size is small (below 0.25 &mgr;m), and the aspect ratio is high (greater than about 3:1), for example, obtaining a continuous seed layer of copper over the feature surface becomes particularly difficult.
FIG. 1A
shows a schematic of a cross-sectional view of a copper-filled semiconductor contact via having a bottom diameter of 0.17 &mgr;m and an aspect ratio of about 7:1, where the step coverage of the copper seed layer is inadequate and the copper fill contains numerous voids. To meet the challenge of filling features having aspect ratios of greater than about 3:1, improvements in step coverage, especially sidewall coverage are required.
SUMMARY OF THE INVENTION
We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. Using a contact via as an example of a high aspect ratio feature, we have demonstrated that despite previously-held views, it is possible to increase the copper seed layer coverage simultaneously at the bottom of the via and on the wall of the via by increasing the percentage of the depositing copper species which are ions. Further, the coverage can be optimized by adjusting the bias voltage of (attractive forces on) the semiconductor substrate surface, as a function of the feature dimensions.
The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. Although the present invention contemplates the use of deposition species of which at least 30% are ions at the time they contact the substrate, for features having a 0.25 &mgr;m or smaller feature size, an aspect ratio of about 3:1 requires that about 50% or more of the copper species be ions at the time of deposition on the substrate. As the aspect ratio increases to about 4:1, the percentage of species which are ions is preferably increased to between about 60% and 70%. When the aspect ratio is abou
Forster John C.
Hashim Imran
Zhang Hong-Mei
Applied Materials Inc.
Bean Kathi
Church Shirley L.
Nelms David
Nhu David
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