Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-09
1999-05-04
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438230, H01L 21336
Patent
active
058997210
ABSTRACT:
A transistor and transistor fabrication method are presented wherein ultra small spacers are formed adjacent sidewall surfaces of a gate conductor. A first dielectric material is deposited over a semiconductor topography. The first dielectric is partially removed to expose a portion of the gate conductor, and a second dielectric material is deposited upon the first dielectric material and the gate conductor. The second dielectric material is anisotropically etched such that the second dielectric material is preferentially removed from substantially horizontal surfaces and retained adjacent substantially vertical surfaces. The first dielectric material is then selectively removed from areas not masked by the second dielectric material. The composite spacers thus formed adjacent sidewall surfaces of the gate conductor are thinner than spacers formed using conventional techniques. Sub-0.25-micron transistors having sidewall spacers formed by the process described herein may be less susceptible to deleterious source-side parasitic resistance than transistors having conventionally formed spacers.
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Gardner Mark I.
Wristers Derrick J.
Advanced Micro Devices , Inc.
Bowers Charles
Chen Jack
Daffer Kevin L.
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