Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-29
2004-07-20
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S369000, C438S506000, C438S527000
Reexamination Certificate
active
06764890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
As is well known, a metal oxide semiconductor field effect transistor (MOSFET) includes a source, a drain, and a gate. The source and the drain are typically formed in a substrate, and separated by a channel. In an enhancement-type MOSFET, a channel sufficient to allow current flow between the source and the drain is not formed until the voltage on the gate relative to the source (v
gs
) equals or exceeds the threshold voltage (V
T
) of the MOSFET.
Complementary metal semiconductor technology (CMOS) allows fabrication and use of two kinds of enhancement-type MOSFET's in the same substrate. The first kind has a P-type channel and is referred to as a “PMOS transistor”, while the second kind has an N-type channel and is referred to as an “NMOS transistor”. PMOS and NMOS transistors may be fabricated in a P-type substrate. In that case, an N-well implant is performed to form an N-well in the region where the PMOS transistor is to be fabricated. The region where the NMOS transistor is to be fabricated is blocked during the N-well implant.
Transistors whose channel is to be formed in a substrate are referred to as “native transistors”, while those whose channel is to be formed in a well are referred to as “well transistors”. In the case where a P-type substrate is employed, the NMOS transistor is the native transistor and the PMOS transistor is the well transistor. To adjust the threshold voltage of a native NMOS transistor, a compensate implant step may be performed after the N-well implant. However, a compensate implant step increases manufacturing costs because it is an additional implant step and requires additional masking steps.
SUMMARY
In one embodiment, the threshold voltage of a first transistor is adjusted by implanting a dopant through a mask (e.g., photoresist material). The thickness of the mask may be varied to obtain a particular threshold voltage. The mask may be formed such that it covers a first transistor region where the first transistor is to be fabricated, while leaving a second transistor region exposed. This allows an implant step to adjust the threshold voltage of the first transistor and to form a well in the second transistor region.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
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Cypress Semiconductor Corporation
Fourson George
Okamoto & Benedicto LLP
Toledo Fernando L.
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