Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
1999-11-15
2002-04-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S795000, C257S787000
Reexamination Certificate
active
06373142
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor chip device assembly, and in particular to flip chip package construction. More specifically, the invention relates to a method of adding filler material to non-filled or low-filled underfill material between the semiconductor chip and substrate using a highly filled fillet during chip packaging.
In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit (IC) chip or “die”) may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g. wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is “flipped” onto its active circuit surface so that the solder balls form electrical connections directly between the chip and conductive traces on a packaging substrate. Semiconductor chips of this type are commonly called “flip chips”.
The initial packaging of the chip occurs in two steps. First, the chip is electrically connected to the substrate and then the chip is mechanically (or adhesively) bonded to the substrate. The chip is electrically bonded to the substrate by applying solder balls to the active circuit surface of the chip. As an example, the solder may be composed of a low melting point eutectic material or a high lead material. Prior to bonding the chip to a substrate, solder flux is applied to either the active surface of the chip or the packaging substrate surface. The flux serves primarily to aid the flow of the solder, such that the solder balls make good contact with traces on the packaging substrate. It may be applied in any of a variety of methods, including brushing or spraying, or dipping the chip into a thin film, thereby coating the solder balls with flux. The flux generally has an acidic component, which removes oxide barriers from the solder surfaces, and an adhesive quality, which helps to prevent the chip from moving on the packaging substrate surface during the assembly process. The flux serves primarily to aid the flow of the solder, such that the solder balls make good contact with traces on the packaging substrate. It should be understood that this electrical bonding also provides a mechanical bond between the chip and substrate.
After the flux is applied, the chip is aligned with and placed onto a placement site on the packaging substrate such that the chip's solder balls are aligned with electrical traces on the substrate. The substrate is typically composed of a laminate or organic material, such as fiber glass, PTFE (such as Teflon™, available from Gore, Eau Claire, Wis.) BT Resin, epoxy laminates or ceramic-plastic composites. Heat, for example, to a temperature of about 220° C., is applied to one or more of the chip and the packaging substrate, causing the solder balls to reflow and form electrical connections between the chip and the packaging substrate. Then, the remaining flux residue is substantially removed in a cleaning step, for instance by washing with an appropriate solvent.
At this point, the mechanical (adhesive) bonding procedure can begin.
FIGS. 1A and B
illustrate the standard underfill method for mechanically bonding the chip and the substrate after the electrical connections between the chip and substrate have been made. In
FIG. 1A
which is a cross-sectional, side view, a chip
100
with an active circuit surface
102
has been electrically connected to a substrate surface
106
via the solder balls
104
. It should be noted that this figure and the figures that follow are intended to be representative and, for example, do not show the solder balls
104
in proportion to the chip
100
. As an example, the chip
100
may have dimensions on the order of 0.5×0.5 inch (1 inch=2.54 cm) whereas the unbonded solder balls
104
may have a diameter on the order of 4 to 5 mils (1 mil=10
−3
inch=0.0254 mm) or less. An underfill material, typically a thermo-set epoxy
108
, such as is available from Hysol Corporation of Industry, Calif. (product numbers 4511 and 4527), Ablestik Laboratories of Rancho Domingo, Calif., and Johnson Matthey Electronics of San Diego, Calif., is dispensed into the remaining space (or “gap”)
110
between the chip
100
and the substrate
106
. In current designs, a representative gap is between 50-75 microns. In a typical procedure, a bead of thermo-set epoxy
108
, is applied along one edge of the chip using an injection mechanism
112
where it is drawn under the chip
100
by capillary action until it completely fills the gap
110
between the chip
100
and the packaging substrate
106
. To assist the flow, slight heating of the packaging substrate after dispensing of the underfill material
108
may be used. In some cases, the underfill material flow is further assisted by vacuum, or, alternatively, by injection of the epoxy into the gap.
To change the coefficient of thermal expansion of the underfill material, a filler material such as alumina or silica is typically added to the underfill material
108
. The spots in the underfill material
108
represent a constant percentage by weight of filler material particles. The filler material, which lowers the coefficient of thermal expansion of the epoxy, increases the rigidity of the cured epoxy which increases the mechanical strength of the bond between the chip and substrate. Thus, the reliability of the packaged system is increased. However, adding filler material to the underfill material reduces the flow rate during the process by which the epoxy is drawn under the chip by capillary action. When the gap between the chip and substrate decreases, the reduced flow rate under the chip increases the possibility of the formation of gaps or voids in the underfill material which reduces the reliability of the packaged chip. An underfill material without any filler material has the best flow rate and thus produces the least amount of gaps and voids. However, using a non-filled underfill material to bond the chip and substrate leads to poor packaging reliability under temperature cycling.
In another mechanical bonding process called no-flow underfill, the underfill material
108
is placed on the package substrate underneath the center of the chip
100
, before the chip
100
is electrically connected to the substrate
106
. In this process, the mechanical bonding and electrical bonding occur in one step. In this process, it is undesirable to add filler material to the underfill material because the filler material adversely affects the electrical connections between the chip and the substrate. Thus, this process is limited to packaging applications where a strong mechanical bond is not required such as for small chips.
As shown in
FIG. 1B
, after the epoxy
108
has bled through the gap
110
, a separate bead of epoxy
114
with the same composition as the underfill material is dispensed and bonded around the perimeter of the chip
100
to create a fillet
112
. The fillet adds additional strength and creates a clean edge around the chip. Thereafter, the epoxy (both the underfill and perimeter bonding epoxy, if any) are cured by heating the substrate and chip to an appropriate curing temperature. In this manner the process produces a mechanically, as well as electrically, bonded semiconductor chip assembly, with the underfill material
108
allowing a redistribution of the stress at the connection between the chip
100
and the substrate
106
from the solder
104
joints only to the entire sub-chip area.
Currently, one disadvantage of the standard underfill method for filling the gap between the chip and the substrate for packaging is that as the gap size approaches 25 microns or less, which is anticipated as requirement for chips in the near future, it becomes very difficult to use underfill material with a high percentage of filler material. With small gaps approaching 25 microns, an underfill material with a high percentage of filler material produces gaps and
Beyer Weaver & Thomas LLP
Clark Sheila V.
LSI Logic Corporation
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