Method for testing the error ratio of a device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S704000, C714S736000, C714S742000

Reexamination Certificate

active

07426664

ABSTRACT:
A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BERlimitwith a early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small probability D. ns bits of the output of the device are measured, thereby ne erroneous bits of the ns bits are detected. PDhighand/or PDloware obtained, whereby PDhighis the worst possible likelihood distribution and PDlowis the best possible likelihood distribution containing the measured ne erroneous bits with the probablility D. The average numbers of erroneous bits NEhighand NElowfor PDhighand PDloware obtained. NEhighand NEloware compared with NElimit=BERlimit×ns. If NElimitis higher than NEhighor NElimitis lower than NElowthe test is stopped.

REFERENCES:
patent: 5396059 (1995-03-01), Yeates
patent: 5606563 (1997-02-01), Dorbolo et al.
patent: 6161209 (2000-12-01), Moher
patent: 6216095 (2001-04-01), Glista
patent: 6526531 (2003-02-01), Wang
patent: 2006/0002460 (2006-01-01), Maucksch et al.
patent: 0 954 117 (1999-11-01), None

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