Method for testing semiconductor chips by means of bit masks

Details Method for testing semiconductor chips by means of bit masks Method for testing semiconductor chips by means of bit masks

2005-11-28

2008-12-02

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S005110, C714S025000, C714S030000, C714S042000, C714S709000, C714S715000, C714S718000, C714S719000, C714S720000, C714S722000, C714S724000, C714S727000, C714S728000, C714S729000, C714S733000, C714S734000, C714S736000, C714S738000, C714S739000, C714S742000, C714S745000, C365S201000

Reexamination Certificate

active

07461308

ABSTRACT:
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

REFERENCES:
patent: 5784382 (1998-07-01), Byers et al.
patent: 6574762 (2003-06-01), Karimi et al.
patent: 6715105 (2004-03-01), Rearick
patent: 7139946 (2006-11-01), Nadeau-Dostie et al.
patent: 7213183 (2007-05-01), Gossman
patent: 2002/0010878 (2002-01-01), Ernst et al.
patent: 2003/0167431 (2003-09-01), Nicolaidis et al.
patent: 2005/0240848 (2005-10-01), Cote et al.
patent: 2006/0156108 (2006-07-01), Stracke et al.
patent: 10102871 (2002-08-01), None
patent: 10124735 (2002-11-01), None
patent: 10223167 (2003-12-01), None
patent: 10231680 (2004-02-01), None

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