Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-05
2004-01-20
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C361S212000, C361S220000, C324S1540PB, C228S004500, C228S013000
Reexamination Certificate
active
06681352
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for testing integrated circuits, and more particularly to methods for testing packaged integrated circuits that have damaged or bent leads.
RELATED ART
Integrated circuits (ICs) are typically tested during several stages of their lifetime. Testing is typically carried out by automatic test equipment (ATE) that includes an IC test signal generator (IC tester) and an interface tool (e.g., a probe card or a test socket). The interface tool is used to provide electrical connections to pads or leads of a device-under-test (DUT), and to route test signals between the DUT and the IC tester. This testing process is typically used to identify non-functional ICs, and is sometimes used to determine why the IC is nonfunctional.
FIG. 1
depicts an ATE arrangement that is utilized during wafer testing procedures performed before a wafer
100
is diced to form individual dies (IC chips)
110
. Each die
110
includes circuitry (not shown) formed on the wafer material that is connected to pads
112
exposed on an upper surface of wafer
100
. An IC tester
10
is used to apply test signals to pads
112
of each die
110
via a probe card
15
-A that includes metal (e.g., tungsten) probes
17
. Typically, wafer
100
is mounted on an X-Y table (not shown) that positions a selected die
110
under probe card
15
-A. Metal probes
17
are then brought into contact with pads
112
. Test signals are then transmitted between IC
110
and IC tester
10
via probe card
15
-A. This wafer testing procedure identifies non-functional die on wafer
100
, which are typically marked using ink or are otherwise identified (e.g., using wafer mapping).
After wafer testing is completed, wafer
100
is then cut (diced) to separate die
110
from each other. The nonfunctional die identified during wafer testing are discarded, and the good (functional) die are sent to a assembly facility for placement into various types of IC packages. The packaged ICs are then returned to the IC tester for operational verification.
FIG.
2
(A) depicts an ATE arrangement that is utilized to test a packaged IC
200
-A. As indicated, packaging involves housing each die
110
in a package body
210
(e.g., plastic) along with a series of metal leads
220
that contact pads
112
and extend from package body
210
. The package type illustrated in FIG.
2
(A) is a dual-in line package (DIP) in which leads
220
-
1
and
220
-
2
extend from opposite sides of package body
210
and are bent downward. For example, lead
220
-
1
includes a stub portion
220
-
1
A extending from package body
210
, and a terminal (arm) portion
220
-
1
B extending downward from a shoulder (bend)
220
-
1
C. During IC testing, arm portions
220
-
1
B are inserted into a test socket
20
that includes a series of contacts
22
for passing test signals between die
110
and IC tester
10
. After testing, good packaged ICs
200
-A are sold to customers, and non-functional ICs are discarded.
ICs occasionally fail after passing all of the tests described above and are sold to customers. These failing parts are sometimes removed from the customer's application and returned to the manufacturer so that the cause of failure can be determined. Unfortunately, many customers lack proper IC removal equipment and procedures, and the returned ICs often include bent or broken leads.
FIG.
2
(B) shows a damaged IC
200
-B in which lead
220
-
1
B is bent inward at shoulder
220
-
1
C such that arm
220
-
1
B fails to align with the underlying contact
22
of test socket
20
. In order to use test socket
20
to determine the cause of failure of damaged IC
200
-B, it is necessary to manually bend arm
220
-
1
B back into its original position. However, this repair process is very time consuming, and may not be possible if arm
220
-
1
B breaks during the bending process. Therefore, the conventional process of testing damaged ICs using test socket
20
is very time consuming, and is sometimes impossible.
What is needed is a method for testing damaged ICs that avoids the problems associated with the prior art.
SUMMARY
The present invention is directed to a method for testing packaged integrated circuits (ICs), and in particular to packaged ICs having damaged (e.g., bent) leads. According to the present invention, instead of attempting to re-bend or otherwise fix the damaged leads, a lower portion of each lead (whether damaged or not) is cut off such that only a stub of lead material is left that is located close to the package body of the IC. The IC is then mounted onto a probe card having upward-facing probes that contact the lead stubs. Test signals are then transmitted between an IC tester and the damaged IC through the probe card. By cutting (removing) the lower portion of each of the leads, a substantial amount of time is saved over prior art methods that require re-bending or otherwise repairing the leads so that the damaged IC can be tested using a test socket.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5029747 (1991-07-01), Russo et al.
patent: 5910878 (1999-06-01), Mello et al.
Beyer Patrick T.
Liu Justin
Moise Emmanuel L.
Xilinx , Inc.
Young Edel M.
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