Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-01-26
2001-02-27
Wiley, David A. (Department: 2155)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S125000
Reexamination Certificate
active
06195757
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to chip technology for computers and like processing systems, and particularly to a system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system.
BACKGROUND OF THE INVENTION
Advances in system chip technology and integration has allowed chips to operate at increasingly higher frequencies. For many systems we find that some of the most critical paths in the system are not on-chip, but between chips. For example the next generation of IBM systems being designed could operate at faster than 4.7 ns. per cycle; but, with the current design for the next generation of chips having physical locations of a multi-chip module (MCM) and memory cards on the same board a delay across the longest nets from say the MCM to a memory card takes a minimum of 5.3 ns. This means that the system can not work at a 5.0 ns cycle time unless other methods are found. Therefore, there is a need to improve on the methods for increasing and maintaining the desired high frequencies of intrachip communication in these future systems, and yet until this invention, the prior attempts fell short.
SUMMARY OF THE INVENTION
We have provided a system enabled by use of our new system communication circuit for providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a multi-chip module and a memory circuit.
The improvements which we have made achieve greatly improved cycle time, as well as a wider range of cycle times which is especially advantageous during machine (a computer or like system processor) bringup and system debug. We have found that our method is much easier to implement than other techniques we have tried, and in addition, our method is independent of the chip process parameters.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
REFERENCES:
patent: 4607348 (1986-08-01), Sheth
patent: 5790614 (1998-08-01), Powell
patent: 5859986 (1999-01-01), Marenin
patent: 5930523 (1999-07-01), Kawasaki et al.
Ingenio Giacomo Vincent
McNamara Timothy Gerard
Meaney Patrick James
Muench Paul David
Augspurger Lynn L.
International Business Machine Corporation
Wiley David A.
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