Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-17
2001-03-27
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S488000, C438S597000, C438S647000
Reexamination Certificate
active
06207483
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of CMOS semiconductor devices and, more particularly to a method for reducing the roughness of undoped polysilicon gate regions of CMOS devices during manufacturing.
BACKGROUND OF THE INVENTION
Excessive surface roughness of polysilicon gate structures in CMOS semiconductor devices may present several problems during both during manufacturing and use. If the gate surface is sufficiently rough, typically in the region of a peak to valley difference approximately 200 Å or greater, subsequent deposition operations may be degraded and, ultimately, device performance and/or reliability affected.
DISCUSSION OF THE PRIOR ART
U.S. Pat. No. 5,851,364 for METHOD FOR FORMING ALUMINUM CONTACTS; issued Dec. 22, 1998 to Jianming Fu, et al. teaches the use of an Argon (Ar) plasma treatment for reducing the surface roughness of a titanium nitride (TiN) contact surface prior to depositing an aluminum contact layer. Better adhesion of the Al to the SiN has been observed, essentially due to better wetting of the surface TiN surface by the Al. The present invention, on the other hand, does not utilize an AR plasma step to improve wetting of a contact pad area but rather uses an Ar plasma sputtering deposition on the surface of an undoped polysilicon gate structure to improve manufacturing and performance characteristics. Reducing the roughness of the gate structure results in improved device performance as shown by I
OFF
vs. I
SAT
and/or V
T
vs. L
EFF
measurements. In addition, the inventive Ar sputtering of the polysilicon gate surface allows subsequent manufacturing steps to be performed in clustered chambers without breaking vacuum which results in higher line throughput with manufacturing economies resulting.
U.S. Pat. No. 5,874,333 for PROCESS FOR FORMING A POLYSILICON LAYER HAVING IMPROVED ROUGHNESS AFTER POCL3 DOPING; issued Feb. 23, 1999 to Chun-Chich Chang, et al. teaches a method for depositing polysilicon. CHANG, et al. teach depositing the polysilicon in two stages. First, an initial deposition takes place at approximately 630°C. until a predetermined layer thickness is achieved. Layer formation in continued without interruption at approximately 560° C. until the final thickness is achieved. This process yields polysilicon layers with improved smoothness because the final, lower temperature deposition stage results in more controlled grain growth. In contradistinction, the inventive process deposits a polysilicon layer at a single temperature. Subsequent to deposition, an Ar plasma sputter is used to smooth the polysilicon surface before any additional wafer processing steps are performed. The inventive process may be performed in such a manner that vacuum is maintained between the Ar sputter and subsequent wafer processing steps, thereby improving process time and lowering processing costs.
U.S. Pat. No. 5,849,628 for METHOD OF PRODUCING ROUGH POLYSILICON BY THE USE OF PULSED PLASMA CHEMICAL VAPOR DEPOSITION AND PRODUCTS PRODUCED BY SAME; issued Dec. 15, 1998 to Gurtej. S. Sandhu, et al. teaches a process for creating a rough polysilicon surface. Reactant gases including Ar and silane are introduced intermittently into the deposition chamber as the polysilicon layer is deposited. This process has been found useful for producing capacitors as part of DRAM devices. The instant invention is, however, directed to a method for smoothing NOT roughing the surface of a polysilicon layer.
U.S. Pat. No. 5,203,957 for CONTACT SIDEWALL TAPERING WITH Argon SPUTTERING; issued Apr. 20, 1993 to Chu-San Yoo, et al. teaches the use of an Ar sputter for reducing corner sharpness at a contact opening, generally a transition point between anisotropically and isotropicallyetched regions. The inventive process, on the other hand, deals with the total surface of an undoped polysilicon gate structure, not just corners. In addition, no post Ar sputter ion etch is performed in the inventive method.
Finally, U.S. Pat. No. 5,888,901 for MULTILEVEL INTERCONNECTION AND METHOD FOR MAKING; issued Mar. 30, 1999 to Gordon M. Grivna teaches a high-pressure sputter etch of a dielectric material such as silicon dioxide between two layers of metalization in a semiconductor structure. A secondary reason is for filling voids in the dielectric with re-deposited silicon dioxide molecules released by the high-pressure Ar sputtering operation. The inventive method, on the other hand, performs a high-pressure Ar sputter in a different manner with a different purpose (i.e., not redeposition of material but rather simply smooth the surface of undoped polysilicon features exposed to the Ar sputter).
Nothing in the above-described or any other known references, taken individually or in any combination, teaches or suggests the unique steps of the present invention.
It is, therefore, an object of the invention to provide a manufacturing step in the production of polysilicon-gate CMOS semiconductors whereby the surface roughness of the gate area is reduced.
It is another object of the invention to provide a manufacturing step in the production of polysilicon-gate CMOS devices which may be performed in clustered chambers on a single mainframe manufacturing line.
It is a still further object of the invention to provide a manufacturing step in the production of polysilicon-gate CMOS devices whereby a MOSFET device having superior electrical performance and/or reliability is achieved.
SUMMARY OF THE INVENTION
The present invention features a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness, either alone in conjunction with a thin capping layer of oxide, nitride or oxynitride.
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patent: 4540607 (1985-09-01), Tsao
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5685941 (1997-11-01), Forster et al.
patent: 5849628 (1998-12-01), Sandhu et al.
patent: 5851364 (1998-12-01), Fu et al.
patent: 5874333 (1999-02-01), Chang et al.
patent: 5888901 (1999-03-01), Grivna
patent: 6057604 (2000-05-01), Nguyen
patent: 0884770 (1998-12-01), None
patent: 11080962 (1999-03-01), None
Chang Chung-Long
Fu Chu-Yun
Jang Syun-Ming
Jeng Shwangming
Ackerman Stephen B.
Pham Long
Saile George O.
Taiwan Semiconductor Manufacturing Company
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