Method for simultaneous deposition and sputtering of TEOS

Details Method for simultaneous deposition and sputtering of TEOS Method for simultaneous deposition and sputtering of TEOS

1998-06-17

2000-11-21

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438624, 438695, 438710, 438788, 438790, H01L 2131, H01L 21469

Patent

active

061502855

ABSTRACT:
A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

REFERENCES:
patent: 5089442 (1992-02-01), Olmer
patent: 5494854 (1996-02-01), Jain
patent: 5814564 (1998-09-01), Yao et al.
patent: 5885894 (1999-03-01), Wu et al.
patent: 5915200 (1999-06-01), Tokumasu et al.
patent: 5968610 (1999-10-01), Liu et al.
Lutze et al. "Techniques for Reducing the Reverse Short Channel Effect in Sub-0.5 micron CMOS", IEEE, pp. 373-375, Sep. 1995.

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