Method for separately optimizing thin gate dielectric of...

Details Method for separately optimizing thin gate dielectric of... Method for separately optimizing thin gate dielectric of...

2003-09-09

2004-11-23

Chaudhuri, Olik (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S775000, C438S769000, C257S369000, C257S410000, C257S405000, C257S411000

Reexamination Certificate

active

06821833

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to the process of manufacture of MOSFET devices and more particularly to the method for manufacture of thin gate dielectric layers for high-performance MOSFET devices.
The scaling of gate dielectric layers to smaller thicknesses is one of the key elements that enables the continued scaling of silicon CMOS technology to higher performance levels. Thinner gate dielectric layers generate more inversion charge, which increases transistor drive current, and also improves short-channel effects by increasing gate control of the channel. Because the gate dielectric layer is formed at the interface where the inversion layer is formed and transistor current is conducted, this must be an extremely high quality interface.
Oxynitrides (SiOxNy) are now widely used in the semiconductor industry as gate dielectric films. The desired properties of gate dielectrics are low gate leakage current, high dielectric constant to increase capacitance, high mobility, high reliability and good diffusion barrier properties. Pure SiO
2
has been the gate dielectric of choice since the early days of the integrated circuit, however, in recent years as gate dielectrics are being scaled into the sub 20 Å thickness range, oxynitrides have been increasingly used in high performance CMOS processes.
Silicon Oxynitrides (SiOxNy) are generated by two general techniques, thermal and plasma nitridation. Thermal nitridation of oxynitrides is carried out by high temperature exposure (650° C.-1000° C.) of a silicon surface, or silicon dioxide (SiO
2
) surface to a reactive nitrogen containing gas such as nitrous oxide (N(
2
O), ammonia (NH
3
), or nitrogen oxide (NO). Thermal energy is used to drive the nitridation reaction. Plasma nitridation of oxynitrides is performed by exposure of a silicon or SiO
2
surface to an activated nitrogen containing plasma. Because the nitrogen has been activated by the plasma, it can react to be incorporated in the oxynitride at lower temperatures than thermal nitridation (anywhere from room temperature to 800° C.). If the plasma nitridation process is performed at a low temperature (e.g. <100° C.), it can be compatible with a photoresist soft-mask process. In this type of low temperature process, the photoresist can be used to selectively block the nitridation from the covered areas, while the exposed areas receive the desired nitrogen incorporation. Thermal processes, as well as high temperature plasma process are not compatible with photoresist. Thermal processes require hard-masks that can withstand high temperatures. Photoresist soft-masking is particularly attractive because resist can be stripped using chemistries that are compatible with gate oxides (e.g. sulphuric acid/hydrogen peroxide (H
2
O
2
) mixtures).
Properly optimized oxynitrides have increased dielectric constants, lower gate leakage current, and improved diffusion barrier properties as compared to pure SiO
2
.
FIG. 1
shows how the gate leakage current decreases with increasing the duration of processing when using a Remote Plasma Nitridation (RPN) process of forming oxynitrides. Often these improvements must be carefully balanced against changes in mobility that may affect the transistor device current. Moreover, this optimization may be different for NFET and PFET devices which reside on the same semiconductor chip. In
FIG. 1
, gate leakage in (amperes/cm−
2
) at 1.2 Volts is shown as a function of T
inv
(Å). The parameter T
inv
is inversion thickness, which is a measure of the effective oxide thickness when the transistor is measured in inversion mode. Units are thickness such as angstroms (Å) or nanometers (nm).
FIGS. 2-3
show examples of how plasma nitridation affects the PFET and NFET device drive current differently. These examples demonstrate that the optimum nitrogen concentration in the gate dielectric is different between the NFET and PFET device, which is generally not known. The vertical axis is Joff and the horizontal axis is Jodlin where Jodlin stands for transistor drain current density (Amperes/&mgr;m), i.e. per unit width of the transistor between the source and the drain. It is a transistor current measured with Vg (gate voltage) a fixed amount above Vt (threshold voltage) to help normalize out any threshold voltage differences. The Joff is a measure of off-state leakage per unit width of the transistor (between the source and the drain) with 0 Volts applied to the gate electrode.
FIGS. 4A-4D
are schematic conceptual diagrams wherein
FIGS. 4A-4D
are views of NFET area
14
and related features taken along section line A-A″ in FIG.
8
A and PFET area
16
and related features taken along section line B-B″ in FIG.
8
A.
FIGS. 4A-4D
show juxtaposed PFET and NFET sectors of a semiconductor device
10
formed in a silicon substrate
12
in four steps of a prior art process, which illustrates how a standard sequence of processing steps of gate dielectric integration results in the same PFET and NFET oxynitride gate dielectric layers
18
N/
18
P for the high-performance transistors with the thinnest gate dielectric layer. This is because when the thin gate dielectric layers
18
N/
18
P are grown, both the NFET area
14
and the PFET area
16
in the substrate
12
are exposed to the same process. This is true whether the process is thermal-based or plasma-based, but a plasma process is shown for illustration.
In
FIG. 4A
, the device
10
is shown in an early stage of manufacture thereof comprising a silicon semiconductor substrate
12
, which has been processed to contain both a P-doped NFET area
14
and an N-doped PFET area
16
in substrate
12
.
In
FIG. 4B
, the device
10
of
FIG. 4A
is shown after a gate oxide layer
18
N has been formed above the top surfaces of the NFET area
14
and gate oxide layer
18
P has been formed above the top surfaces of the PFET area
16
.
In
FIG. 4C
, the device
10
of
FIG. 4B
is shown after the gate oxide layers
18
N/
18
P have been treated with a uniform plasma nitridation by driving nitrogen into the gate oxide layers
18
N/
19
P above the top surfaces of the NFET area
14
and the P-doped PFET area
16
. The same is true for a thermal nitridation.
In
FIG. 4D
, the device
10
of
FIG. 4C
is shown with the identical gate dielectric layers
18
A in place of gate oxide layers
18
N/
18
P. The identical gate dielectric layers
18
A have been shaded with horizontal dash lines to show the transformation of the gate oxide layers
18
N/
18
P into the identical gate dielectric layers
18
A as a result of the uniform nitridation of the gate dielectric layers
18
N/
18
P of
FIG. 4C
above the top surfaces of the NFET area
14
and the PFET area
16
. Please note that
FIG. 4D
is composed of sections taken along lines A-A″ and B-B″ in FIG.
8
A.
Because the optimum oxynitride is different for NFET and PFET devices, it is highly desirable to optimize the two separately, since the overall CMOS integrated circuit performance is determined by both NFET and PFET device performance. If the same gate dielectric layers
18
N/
18
P were grown over NFET area
14
and the PFET area
16
at the same time, one device will be optimized, while the other will be sub-optimum. The fact that there is a suboptimum device may limit the overall CMOS circuit performance of the product.
U.S. Pat. No. 6,093,661 of Trivedi et al entitled “Integrated Circuitry And Semiconductor Processing Method of Forming Field Effect Transistors” teaches nitrogen atom concentration peaking at any elevational location in the gate dielectric layers of the device, but preferably at a location in the gate dielectric layers proximate the lower interface between the gate dielectric layers and the P and N doped regions of a monocrystalline silicon semiconductor substrate. Preferably, the concentration of nitrogen atoms is from 0.1% to 10.0% molar in the peak elevation region in the gate dielectric layer, preferably from 0.5% to 5.0% molar, with a thickness for the peak elevation region from 30 Å to 6

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