Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-19
2002-08-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000
Reexamination Certificate
active
06436760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor device fabrication, and more particularly to a method for removing surface oxide layers from polysilicon material. The invention also relates to a method for making a trench capacitor which has improved performance as a result of surface oxide removal.
2. Description of the Related Art
Polysilicon is a commonly used material in semiconductor devices. It is used to form, for example, the gate structure of deep trench capacitors in dynamic random access memory (DRAM) cells, thin film capacitors in high-density static random access memory (SRAM) and video display devices, emitters of bipolar transistors, and conductive glue layers in devices such as solar cell panels.
One problem of using polysilicon is that it easily oxidizes in air. The resulting silicon oxide is insulating and therefore creates a high contact resistance between the polysilicon and subsequent contacts.
Conventionally, surface oxide is removed from polysilicon by dipping the semiconductor wafer in an HF bath. The wafer is the washed in DI water and then dried before subsequent processing of the polysilicon. This approach is undesirable because after the HF dip is performed, the wafer must be processed within a short time window or the oxide will re-grow. In fact, as soon as the wafer is removed from the HF bath, a very thin native oxide will immediately grow on the polysilicon.
Techniques have been proposed for removing the residual native oxide after HF dip. One technique involves performing a hydrogen bake at a pressure of 1 Torr for 15 minutes at 900° C. See, for example, “Improved Control of Polysilicon Emitter Interfacial Oxide using a UHV-Compatible LPCVD Cluster Tool” by A. I. Abdul-Rahim, C. D. Marsh, P. Ashburn, and G. R. Booker, IEEE/MTT/ED/AP/LEO Societies Joint Chapter United Kingdom and Republic of Ireland Section, and 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronics Applications. EDDO London, UK Nov. 24-25, 1997, p 232-6. There are two drawbacks to this approach. First, hydrogen can diffuse into the device, thereby causing a shift in its electrical characteristics. Second, the relative long bake at 900° C. causes redistributions of dopants which affects the device characteristics.
Removal of surface oxide from polysilicon is especially important in improving the quality of conductor plates in trench capacitors. The conventional approach to fabricating these plates involves filling the trench halfway with arsenic (As)-doped polysilicon, depositing a collar oxide, and then filling the remainder of the trench with more heavily doped polysilicon after etching away the top oxide layer on the surface of the bottom polysilicon.
Because of the faster oxidation rate of doped polysilicon compared with amorphous silicon, additional oxide is formed on the polysilicon at the bottom half of the trench. Complete removal of this oxide without sacrificing the collar oxide is very difficult due to the small opening and high aspect ratio of the trench. The oxide remaining at the two polysilicon interfaces creates a high contact resistance which degrades the performance of the overall device. For example, in the case where the trench capacitor is employed as a DRAM capacitor, this high contact resistance significantly limits the charging and discharging speeds of the DRAM cells.
In view of the foregoing considerations, it is therefore clear that a need exists for a better method of removing oxide from polysilicon during semiconductor device fabrication, and moreover one which may be used to form a trench capacitor with less contact resistance and faster charging/discharging times than conventional devices of this type.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide an improved method for removing oxide from polysilicon during semiconductor device fabrication.
It is another object of the present invention to achieve the first object by depositing a barrier layer on the polysilicon that will enable a complete removal of surface oxide on the polysilicon.
It is another object of the present invention to provide a method for removing oxide from polysilicon which does not require the polysilicon to be processed after HF dip within any time window, let alone a short time window as conventional methods require in order to prevent re-growth of surface oxide on the polysilicon, thereby making the invention easier to implement compared with these conventional methods.
It is another object of the present invention to provide a method for removing oxide from polysilicon which provides enhanced protection for wafers during polysilicon deposition in vertical furnaces without load lock.
It is another object of the present invention to apply the aforementioned method to form the conductor plates of a trench capacitor, which conductor plates allow the trench capacitor to realize faster charging and discharging times.
It is another object of the present invention to provide a method for forming a trench capacitor which has less contact resistance than capacitors made by conventional methods, wherein the reduced contact resistance is achieved by filling the trench with heavily doped silicon-germanium material instead of doped polysilicon.
The foregoing and other objects of the invention are achieved by providing a method for removing surface oxide from polysilicon during semiconductor device fabrication. The method includes depositing a barrier layer on the surface oxide layer, baking the polysilicon, surface oxide, and barrier layers until the barrier layer reacts with the surface oxide layer to form a volatile sub-oxide layer, and then subliming the sub-oxide layer away, As a result of these steps, the surface of the polysilicon layer is completely oxide-free. The barrier layer may include one or more monolayers of germanium. In an optional step, a second polysilicon layer is deposited on the oxide-free surface of the first polysilicon layer, to thereby form an oxide-free polysilicon-polysilicon interface. Such an interface is highly desirable in integrated circuit devices because it reduces contact resistance, thereby improving device performance. Alternatively, doped amorphous silicon or doped amorphous SiGe layers may be deposited in place of the polysilicon layers. As used herein, and in the claims appended herein, amorphous silicon and amorphous SiGe are deposited silicon which may be deposited in place of deposited polysilicon
The method continues by depositing a second polysilicon layer on the oxide-free surface of the first polysilicon layer. Like the first polysilicon layer, the second polysilicon layer also has a surface oxide when initially formed. To remove this oxide, a barrier layer is deposited on the surface oxide layer of the second polysilicon layer, and then the layers are baked until the barrier layer reacts with the surface oxide layer to form a volatile sub-oxide layer. The sub-oxide layer is then removed by subliming leaving the second polysilicon layer with an oxide-free surface. A third polysilicon layer may then be deposited on the second polysilicon layer. In the foregoing steps, the barrier layers may be made from germanium and in place of the polysilicon layers, doped amorphous silicon or doped amorphous SiGe maybe deposited. The resulting oxide-free interfaces between the deposited silicon layers advantageously reduce contact resistance and increases charge/discharge times of the resulting device thereby outperforming conventional trench capacitors
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K. Prabhakaran et al, O
Chakravarti Ashima B.
Chakravarti Satya N.
Iyer Subramanian S.
Wong Kwong H.
Dang Phuc T.
McGuire Woods LLP
Neff Darryl L.
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