Method for reducing capacitance in metal lines using air gaps

Details Method for reducing capacitance in metal lines using air gaps Method for reducing capacitance in metal lines using air gaps

1999-12-21

2001-09-18

Padgett, Marianne (Department: 1762)

Coating processes

Direct application of electrical, magnetic, wave, or...

Plasma

C427S574000, C427S569000, C438S763000, C438S788000

Reexamination Certificate

active

06291030

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to metal interconnects, and more particularly, to a method for reducing capacitance between the lines of a metal interconnect.
2. Background Information
In semiconductor integrated circuit (IC) fabrication, metal lines are deposited to interconnect IC components and to connect IC components to pads. The metal lines are formed by the physical deposition (such as by sputtering) of a layer of metal (such as aluminum or an aluminum-copper alloy). The metal layer is then patterned and etched to form the desired interconnect pattern.
The “metal layer” is also referred to as a metal interconnect. Once the metal interconnect has been deposited and etched, a dielectric layer, commonly known as an interlayer dielectric (ILD), is deposited over the metal layer to insulate the metal layer from subsequently deposited conductive structures or layers.
FIG. 1
shows a typical prior art process of forming the interlayer dielectric over the metal interconnect structure. Specifically, in
FIG. 1
, a metal interconnect
101
is formed atop of a substrate
103
. The term substrate as used herein refers to not only a semiconductor substrate, but may also refer to any intermediate structures, conductive layers, dielectric layers, or any other semiconductor structure that is underneath the metal layer
101
.
Typically, in the prior art, a high-density plasma chemical vapor deposition (HDPCVD) oxide
105
is formed over the metal lines
101
. Characteristically, the HDPCVD oxide
105
forms peaks over the metal lines. Next, a cap oxide layer
107
is formed over the HDPCVD oxide
105
. The cap oxide layer
107
is formed by plasma enhanced chemical vapor deposition (PECVD). Turning to
FIG. 2
, after the cap oxide layer
107
is deposited, a planarization step, typically by chemical mechanical planarization (CMP), is used to planarize the cap oxide layer
107
.
As the dimensions of integrated circuits decrease down to 0.15 microns and below, capacitance that is formed between adjacent metal lines
101
and between a metal line and the underlying substrate can be a performance limiting factor. Specifically, turning to
FIG. 3
, the conductive structures are shown in schematic form with the metal lines identified by reference numeral
101
. The center metal line
101
b
creates a capacitance with its two neighboring adjacent metal lines
101
a
and
101
c.
In addition, the center metal line
101
b
creates a capacitance with any conductive structures in the substrate.
As can be appreciated by those skilled in the art, the capacitance is directly related to the distance between the conductive structures. As this distance becomes smaller, the capacitance increases. This capacitance tends to slow or impede the flow of signals along the metal lines due to the RC delay.
The most popular material used for ILD comprises silicon dioxide, which has a dielectric constant of about 3.9. One prior art method to reduce capacitance is to utilize low-k dielectrics, such as a fluorine-doped oxide. However, this technology is not well developed and may cause other problems in the manufacturing process.
Further, it has been contemplated to form air gaps between the metal lines. Because air has the lowest dielectric constant of 1, this will lower the capacitance between metal lines if air gaps are inserted between the metal lines. The conventional air gap structure is formed by depositing a layer of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide to form the air gaps, followed by a high density plasma chemical vapor deposition (HDPCVD) silicon dioxide process. Finally, a cap oxide layer is deposited and a chemical mechanical polishing (CMP) is performed. However, the CMP process will cause problems with the ILD structure if performed incorrectly.
Thus, what is needed is a new method to produce air gaps between metal lines to reduce the capacitance between metal lines for very narrow distances between the metal lines.
SUMMARY OF THE INVENTION
A method for forming a metal interconnect having a plurality of metal lines and an interlayer dielectric is disclosed. The metal interconnect has a decreased capacitance between the metal lines of the metal interconnect. First, a metal interconnect is formed onto a substrate. A first HDPCVD oxide layer is formed over the metal interconnect. A second HDPCVD oxide layer is formed over the first HDPCVD oxide layer, the second HDPCVD oxide layer being formed such that air gaps are formed between the metal lines of the metal interconnect. Furthermore, a third HDPCVD oxide layer may be formed over the second HDPCVD oxide layer, the third HDPCVD oxide formed using a sputter to deposition ratio higher than that used to form the second HDPCVD oxide layer.


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