Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-16
2002-04-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C438S594000
Reexamination Certificate
active
06376309
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory devices, and more particularly to the gap filling between cells after a spacer etch.
BACKGROUND OF THE INVENTION
Semiconductor memory devices include flash memory devices.
FIG. 1
illustrates a cross-section of two conventional memory cells
100
and
150
in a core area of a flash memory device. The cells
100
,
150
are comprised of tunnel oxides
104
on a substrate
102
and floating gates
106
composed of polysilicon on the tunnel oxide
104
. The control gates comprise polysilicon layers
110
and tungsten silicide layers
112
on the polysilicon layers
110
. Dielectric layers
108
insulate the floating gates
106
from the control gates
110
and
112
. The control gates
110
and
112
are coupled to a word line. Cap layers
114
composed of silicon oxynitride reside on the control gates
110
and
112
and provide an anti-reflective coating at masking. To prevent charge leakage, spacers
116
comprising oxide are formed at each side of the floating gates
106
. The gaps between the cells
100
,
150
are filled by an oxide (
118
of FIGS.
2
A and
2
B).
An important characteristic of the cell structure is the gate aspect ratio. Gate aspect ratio refers to the ratio of the height of the stack structures A and the distance between the stack structures of adjacent cells B, i.e., A/B. The larger the gate aspect ratio, the more difficult it is to completely fill the gap between the cells with the oxide. If the gate aspect ratio is too high, then bad step coverage by the oxide results. Bad step coverage can create voids, as illustrated in
FIG. 2A
, or seams, as illustrated in
FIG. 2B
, in the oxide
118
. Voids and seams create weaknesses in the oxide film
118
, reducing the reliability of the device.
Accordingly, there exists a need for a method for reducing the gate aspect ratio of a flash memory device. The method should improve the step coverage of the oxide between spacers of adjacent cells of the device. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
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patent: 5801415 (1998-09-01), Lee et al.
patent: 5879991 (1999-03-01), Lui et al.
patent: 5897354 (1999-04-01), Kachelmeier
patent: 6034401 (2000-03-01), Hsia et al.
patent: 6133602 (2000-10-01), Shrivastava et al.
Chang Kent Kuohua
Fang Hao
Wang John JianShi
You Lu
Advanced Micro Devices , Inc.
Fourson George
Garcia Joannie Adelle
Sawyer Law Group LLP
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