Method for providing a cell-based ASIC device with multiple...

Details Method for providing a cell-based ASIC device with multiple... Method for providing a cell-based ASIC device with multiple...

2005-09-13

2005-09-13

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06944843

ABSTRACT:
A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M1. All fast or high-power circuits are grouped together into high-power logic blocks and synthesized with high-power circuit macro libraries. All slow or low-power circuits are grouped together into low-power logic blocks and synthesized with low power circuit macro libraries. The associate power and ground buses are applied to metal layer M1in each of the logic blocks. The logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell. The ASIC is then routed and tested before the mask is released.

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patent: 6466054 (2002-10-01), Kameyama et al.
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patent: 6710621 (2004-03-01), Devlin et al.
patent: 6747478 (2004-06-01), Madurawe
patent: 2003/0101307 (2003-05-01), Gemelli et al.

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