Jai P. Bansal

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Gate array core cell for VLSI ASIC devices

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate

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High voltage tolerant off chip driver circuit

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate

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Latent image ram cell

Static information storage and retrieval – Read only systems – With override
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Method for designing structured ASICS in silicon processes...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Method for providing a cell-based ASIC device with multiple...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Profile ID: LFUS-PAI-P-469388

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