Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2002-06-25
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S242000, C438S246000, C438S257000
Reexamination Certificate
active
06410391
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a method for fabricating an EEPROM (electrically erasable programmable read only memory) memory cell.
In EEPROMs, a storage capacitor is charged and discharged with a floating gate through a tunnel oxide, the threshold voltage of an associated transistor changing as a result of this.
The present invention and the problems on which it is based will be explained below with regard to a trench capacitor used in a DRAM memory cell. Such memory cells are used in integrated circuits (ICs), such as, for example, random access memories (RAMs), dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs). Other integrated circuits contain logic devices, such as, for example, programmable logic arrays (PLAs), application-specific ICs (ASICs), mixed logic/memory ICs (embedded DRAMs) or other circuit devices. It is usual for a multiplicity of ICs to be fabricated in parallel on a semiconductor substrate, such as, for example, a silicon wafer. Alter processing, the wafer is decided in order to separate the ICs into a multiplicity of individual chips. The chips are then packaged into end products, for example for use in consumer products such as, For example, computer systems, celluar telephones, personal digital assistants (PDAs) and further products. For discussion purposes, the invention wilt be described with regard to the formation of an individual memory cell.
Integrated circuits (ICs) or chips use capacitors for the purpose of storing charge. One example of an IC which uses capacitors to store charges hs a memory IC, such as, for example, a chip for a dynamic read/write memory with random access (DRAM). The charge state (“0” or “1”) in the capacitor represents a data bit in this case.
A DRAM chip contains a matrix of memory cells which are connected up in the form of rows and columns. The row connections are usually referred to as word lines and the column connections as bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions separated by a channel above which a gate is arranged. Depending on the direction of the current flow, one diffusion region is referred to as the drain and the other as the source. The designations “drain” and “source” are used mutually interchangeably here with regard to the diffusion regions. The gates are connected to a word line, and one of the diffusion regions is connected to a bit line. The other diffusion region is connected to the capacitor. The application of a suitable voltage to the gate switches the transistor on and enables a current flow between the diffusion regions through the channel in order thus to form a connection between the capacitor and the bit line. The switching-off of the transistor disconnects this connection by interrupting the current flow through the channel.
The charge stored in the capacitor decreases with time on account of an inherent leakage current. Before the charge has decreased to an indefinite level (below a threshold value), the storage capacitor must be refreshed.
Ongoing endeavors to reduce the size of storage devices foster the design of DRAMs having a greater density and a smaller characteristic size, that is to say a smaller memory cell area. In order to fabricate memory cells which occupy a smaller surface region, smaller components, for example capacitors, are used. However, the use of smaller capacitors results in a reduced storage capacitance, which, in turn, can adversely affect the functionality and usability of the storage device. For example, sense amplifiers require a sufficient signal level for reliable read-out of the information in the memory cells. The ratio of the storage capacitance to the bit line capacitance is critical in determining the signal level. If the storage capacitance becomes too small, this ratio may be too small to generate a sufficient signal. Likewise, a smaller storage capacitance requires a higher refresh frequency.
One type of capacitor usually used in DRAMs is a trench capacitor. A trench capacitor has a three-dimensional structure formed in the silicon substrate. An increase in the volume or the capacitance of the trench capacitor can be achieved by etching more deeply into the substrate. In this case, the increase in the capacitance of the trench capacitor does not have the effect of enlarging the surface occupied by the memory cell.
A customary trench capacitor contains a trench etched into the substrate. This trench is typically filled with n
+
-doped polysilicon, which serves as one capacitor electrode (also referred to as storage capacitor). Optionally, a second capacitor electrode (also referred to as “buried plate”) is formed by outdiffusion of n
+
-dopants from a dopant source into a region of the substrate which surrounds the lower portion of the trench. An n
+
-doped silicate glass, such as, for example, an arsenic-doped silicate glass (ASG), serves as the dopant source in this case. A storage dielectric containing nitride is usually used to insulate the two capacitor electrodes.
A dielectric collar is produced in the upper region of the trench in order to prevent a leakage current from the capacitor connection with the buried plate. The storage dielectric in the upper region of the trench, where the collar is to be formed, is removed before said collar is formed. The removal of the nitride prevents a vertical leakage current along the collar.
However, the removal of the upper region of the nitride layer creates pinholes at the transition between the lower part of the collar and the upper part of the storage dielectric. Such pinholes impair the quality of the storage dielectric and are a significant source for the charge dissipation from the trench. This reduces the retention time of the trench capacitor and consequently impairs its functionality.
In order to prevent the formation of pinholes, a two-stage trench etching process has been proposed. It this case, first of all the trench is partly etched by reactive ion etching (RIE) down to the depth of the collar. The reactive ion etching is selective with regard to the etching hard mask used. The chemicals usually used for reactive ion etching comprise NF
3
/HBr/He/O
2
, for example. An oxide layer is then deposited and etched in such a way that it forms the collar on the trench sidewalls. The reactive ion etching is selective with regard to silicon if, for example, the chemicals CHF
3
/He/O
2
, CHF
3
/Ar, C
4
F
8
/Ar or CF
4
are used. The remaining region of the trench is etched once the collar has been formed. The storage dielectric is then formed over the collar and the lower region of the trench sidewalls. This method obviates the need for eliminating the upper region of the storage dielectric and hence the formation of pinholes.
Although such a two-stage trench formation process is helpful in preventing pinholes, the second reactive ion etching step for removing silicon can cause excessive erosion of the collar. Such impairment of the collar causes leakage currents to occur. Furthermore, the collar serves as an etching hard mask for the second reactive ion etching step for the purpose of fabricating the trench, which creates a lower portion of the trench with a diameter which is equal to the internal diameter of the collar. Consequently, the lower region of the trench is smaller than the upper region, which has a diameter which is approximately equal to the external diameter of the collar. This is undesirable since the capacitance of the capacitor is consequently reduced.
A customary DRAM cell will now be described with reference to
FIG. 7 and a
variant of the method for fabricating the DRAM memory cell according to
FIG. 7
will be described with reference to
FIGS. 8
a-g.
The trench capacitor according to
FIG. 7
contains a storage dielectric
164
, which is formed in stepped fashion
Brophy Jamie L.
Greenberg Laurence A.
Infineon - Technologies AG
Jr. Carl Whitehead
Locher Ralph E.
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