Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-09-24
1998-05-19
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438552, H01L 218238
Patent
active
057535485
ABSTRACT:
A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.
REFERENCES:
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5439834 (1995-08-01), Chen
S. Wolf, "Silicon Processing In The VLSI ERA vol. 2" Lattice Press, Sunset Beach, CA, p. 398, (1990).
Chen Pei-Hung
Chiang An-Min
Wann Yeh-Jye
Yu Shau-Tsung
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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