Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-04-05
2005-04-05
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S745000, C216S058000
Reexamination Certificate
active
06875699
ABSTRACT:
A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.
REFERENCES:
patent: 6051282 (2000-04-01), Konjuh et al.
patent: 6057239 (2000-05-01), Wang et al.
patent: 6214526 (2001-04-01), Sundararajan et al.
patent: 6251770 (2001-06-01), Uglow et al.
patent: 6537923 (2003-03-01), Bhatt et al.
patent: 6613691 (2003-09-01), Hung et al.
U.S. Appl. No. 09/972,765, entitled “Trench Etch Process for Low-K Dielectrics”, by inventors Li et al., filed Oct. 5, 2001.
U.S. Appl. No. 09/888,279, entitled “Low Dielectric Constant Insulators and Supporting Layers Patterned by Deep Ultraviolet Photolithography”, by inventors Mountsier et al., filed Jun. 21, 2001.
U.S. Appl. No. 09/990,197, entitled “Applications and Methods of Making Nitrogen-Free Anti-Reflective Layers for Semiconductor Processing”, by inventors Van Schravendijk et al., filed Nov. 21, 2001.
Ogawa et al., article entitled “Practical Resolution Enhancement Effect by New Complete Anti-Reflective Layer in KrF Excimer Laser Lithography”, Optical/Laser Microlithography, Session VI, vol. 1927 (1993).
T. Perera, article entitled “AntiReflective Coatings: An Overview”, Solid State Technology, vol. 37, No. 7, pp. 131-136 (1995).
Chi Chiu
Lassig Stephan
Li Si Yi
Mountsier Thomas W.
Pohray Vinay
Beyer Weaver & Thomas LLP
Lam Research Corporation
Novellus Sytems, Inc.
Vinh Lan
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