Method for patterning a feature using a trimmed hardmask

Details Method for patterning a feature using a trimmed hardmask Method for patterning a feature using a trimmed hardmask

2005-07-05

2005-07-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S717000, C438S585000, C438S151000

Reexamination Certificate

active

06913958

ABSTRACT:
In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.

REFERENCES:
patent: 6750127 (2004-06-01), Chang et al.
patent: 6759286 (2004-07-01), Kumar et al.
patent: 6797552 (2004-09-01), Chang et al.
patent: 2004/0043590 (2004-03-01), Bonser et al.
patent: 2004/0087092 (2004-05-01), Huang et al.

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