Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Utility Patent
1998-07-27
2001-01-02
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000, C714S738000, C324S073100, C324S537000, C324S763010
Utility Patent
active
06170071
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to the testing of digital integrated circuits by Automated Test Equipment (ATE). Specifically, the invention relates to assignments from tester channels on ATEs to signal pins on device under test.
BACKGROUND OF THE INVENTION
The use of ATEs for digital Integrated Circuit (IC) testing is widely known in the art. A typical ATE has many tester channels or resources which are connected to signal pins on the device under test (DUT).
Prior art design of ATE designs have arbitrary assignment of the signal pins on the DUT to the tester channels on ATEs. That is, irrespective of the layout of the pins on the DUT, the prior art design utilizes a standard and random assignment scheme for assigning tester channels on the ATE to the signal pins on the DUT.
Such a channel assignment scheme slows the performance of the ATEs as it creates unnecessary overhead requirements on the execution time of the ATEs. The execution time of any ATE test machine comprises overhead time plus actual test time for testing the DUT. The overhead time is the time spent performing some function other than actual testing of the DUT, and includes for example, the loading of test vector sets into vector memory before the actual testing can take place.
In prior art ATEs, especially in ATEs with bus architectures, the overhead time for loading test vector sets into the vector memory is usually many times longer than the actual test time.
For example, in a typical ATE, the channels are arranged in channel groups wherein each single group is made of eight channels. In these particular ATEs, the test vectors are loaded into memory by sequential loading of channel groups. ATEs load one group at a time, i.e., eight bits per clock cycle, wherein each group is made of eight channels. Thus, ideally, if 128 signal pins need to be tested, correspondingly, 128 channels need to be loaded. As channels are loaded in channel groups of eight, only 16 vector set loads will be required.
However, in the prior art design, this is not the case as signal pins have been randomly assigned to various channel groups. For example, signal pin number
1
may have been assigned to channel group number
3
; signal pin number
2
may have been assigned to channel group number
4
; signal pin number
3
may have been assigned to channel group number
1
. ATEs load vector data by loading the channel groups by the order of channel group numbers. The whole group is loaded at once regardless of how many channels in that group are actually loaded. For instance, ATE would first load channel group number
1
, therefore, data for signal pin number
3
will be loaded. Then data for channel group number
3
will be loaded, therefore data for signal pin number
1
will be loaded. And then channel group number
4
is to be loaded, therefore data for signal pin number
2
will be loaded.
This shows the inefficiency in prior art design. To test three signal pins, three different channel groups were loaded. Had signal pins been assigned in a systematic manner by first completing assignments to the first channel group, only one data load (channel group number
1
) would have been required.
Thus, there exists a need for an improved method for tester channel assignment which reduces overhead time of ATEs thereby causing a significant cost savings.
SUMMARY OF THE INVENTION
The present invention offers a systematic method for assigning tester channels on ATEs to various signal pins on DUTs. The method involves creating a test fixture or a load board for a digital IC by wiring the DUT pins to as few channel groups as possible.
The inventive method calculates the number of channel groups required for each vector set load before the signal pins are assigned. Then, the signal pins are assigned in a systematic manner to the fewest number of channel groups.
As the number of test channel groups is reduced, the amount of vector data loaded into the tester's vector memory before each test vector is executed also is reduced, therefore reducing the time and cost required to test the signal pins on the DUT.
REFERENCES:
patent: 4348759 (1982-09-01), Schnurmann
patent: 4724379 (1988-02-01), Hoffman
patent: 5014002 (1991-05-01), Wiscombe et al.
patent: 5432797 (1995-07-01), Takano
patent: 5537052 (1996-07-01), Wilson et al.
patent: 5673272 (1997-09-01), Proskauer et al.
patent: 5701309 (1997-12-01), Gearhardt et al.
Lucent Technologies - Inc.
Moise Emmanuel L.
Synnestvedt & Lechner LLP
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