Method for multi-bit parallel test in semiconductor memory devic

Details Method for multi-bit parallel test in semiconductor memory devic Method for multi-bit parallel test in semiconductor memory devic

1990-07-30

1991-12-31

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518901, G11C 1300

Patent

active

050776894

ABSTRACT:
A method for performing a multi-bit parallel test in a semiconductor memory device having a data output buffer and a given number of data bus pairs and memory cell groups. The semiconductor memory device further includes a data sensing circuit for sensing each pair of data supplied from the memory cell groups; a driver coupled between the data sensing circuit and the given number of data bus pairs; first comparators coupled between the data sensing circuit and a corresponding one of the data bus pairs; a second comparator having inputs coupled to the data bus pairs and an output connectable to the data output buffer; and a data selection circuit having inputs coupled to the data bus pairs and an output coupled to the data output buffer. The data sensing circuit delivers to the data bus pairs a plurality of data pairs from the memory cell group, through the driver upon a normal mode, whereas the data sensing circuit delivers the plurality of data pairs to the first comparator upon a second mode.

REFERENCES:
patent: 4977542 (1990-12-01), Matsuda et al.

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