Method for microprocessor test insertion reduction

Details Method for microprocessor test insertion reduction Method for microprocessor test insertion reduction

2006-03-07

2006-03-07

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S037000

Reexamination Certificate

active

07010734

ABSTRACT:
Methods for reducing the requirement for multiple test vector sub-set insertions of a test vector set on test equipment having a limited memory size. In one embodiment, a single, selective test vector sub-set is utilized in the pre-burn-in test phase of microprocessors and multiple test vector sub-set insertions of a test vector set are utilized in the post-burn-in test phase. In one embodiment, the single, selective test vector sub-set includes selected test vectors from some or all of the test vector sub-sets used in the post-burn-in test phase and is sized to fit within the fixed memory capacity of the test equipment. In another embodiment, a single, selective test vector sub-set is utilized in both the pre-burn and post-burn test phases.

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