Method for manufacturing two-bit flash memory

Details Method for manufacturing two-bit flash memory Method for manufacturing two-bit flash memory

1999-10-28

2001-04-10

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S591000

Reexamination Certificate

active

06214672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a flash memory. More particularly, the present invention relates to a method for manufacturing a two-bit flash memory.
2. Description of Related Art
A conventional flash memory is a type of erasable programmable read-only memory (EPROM), which in turn is a type of non-volatile memory. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore. the speed of memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. For most other EPROM, memory erasure can take up to several minutes due to its bit-by-bit operation.
Typically, flash memory is constructed from a metal-oxicle-semiconductor transistor with an electrically changeable threshold voltage. The silicon nitride oxide semiconductor (SNOS) is one kind of flash memory.
FIG. 1
is a schematic, cross-sectional view of a conventional two-bit SNOS memory. The components of the SNOS memory comprise a source/drain region
102
formed in the substrate
100
, a thin oxide layer
104
formed on a portion of the substrate
100
between the source/drain regions
102
and a silicon nitride layer
106
formed on the thin oxide layer
104
. This structure further comprises a polysilicon gate
108
formed on the silicon nitride layer
106
.
When the flash memory stores data, a high voltage is applied to the source/drain region
102
and the polysilicon gate
108
to induce hot electrons. The hot electrons flow from the source/drain region
102
and vertically penetrate through the thin oxide layer
104
near the source/drain region
104
to be trapped in a portion of the nitride layer
106
near the source/drain region
102
. Therefore, each end of the silicon nitride layer
106
stores one bit. Specifically, a SNOS memory cell can store two bits.
However, the hot electrons trapped in the silicon nitride layer
106
are unstable at both ends of the silicon nitride layer
106
. It is easy to induce a redistribution effect of the hot electrons, so that the hot electrons spread over the silicon nitride layer
106
. The hot electrons respectively injected from the source region and the drain region are remixed and spread over the silicon nitride layer
106
. Hence, the operation performance of the flash memory is restricted and the problem of over-programming occurs.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a two-bit flash memory. A substrate is provided. The substrate has a thin oxide layer, a silicon nitride layer and a material layer formed thereon in sequence. An opening is formed in the material layer and the silicon nitride layer to expose a portion of the thin oxide layer. A source/drain region is formed in the substrate beneath the portion of the thin oxide layer exposed by the opening. A first dielectric layer is formed in the opening. A portion of the material layer and a portion of the silicon nitride layer are removed to form a spacer on the sidewall of the first dielectric layer. The remaining material layer is removed. A portion of the thin oxide layer exposed by the remaining silicon nitride layer and the first dielectric layer is removed. A second dielectric layer is formed on a portion of the substrate exposed by the remaining thin oxide layer. A control gate is formed over the substrate.
In the invention, the silicon nitride layer is separated by a dielectric layer into two silicon nitride layers, each used to store one bit. Since the two silicon nitride layers are electrically isolated from each other by the dielectric layer, the two-bit storage and the over-programming problems can be overcome.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4306353 (1981-12-01), Jacobs et al.
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 5387534 (1995-02-01), Prall

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