Method for manufacturing split-gate flash memory cell

Details Method for manufacturing split-gate flash memory cell Method for manufacturing split-gate flash memory cell

1998-04-16

2000-11-07

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, 438266, 438593, 257314, 257316, 257319, H01L 21336, H01L 214763

Patent

active

061436062

ABSTRACT:
In this method for manufacturing a split-gate flash memory cell, a floating gate and a control gate are formed over a substrate, and then first spacers are formed on the sidewalls of the gate structure. Next, a polysilicon layer is deposited over the gate structure and the substrate, and second spacers are formed on the sidewalls of the polysilicon layer. A self-aligned ion implantation process is performed, using the second spacers as a mask, implanting ions into the semiconductor substrate to form a drain region. This maintains the channel length. After removing the second spacers, another ion implantation process is performed to create a source region in the semiconductor substrate. During the second implantation, the polysilicon layer offers some protection for the semiconductor substrate, maintaining the capacity for tunneling. Finally, a conductive layer is formed over the polysilicon layer, and the conductive layer combined with the polysilicon layer forms the select gate.

REFERENCES:
patent: 5494838 (1996-02-01), Chang et al.
patent: 5674768 (1997-10-01), Chang et al.
patent: 5856223 (1999-01-01), Wang
patent: 5963806 (1999-10-01), Sung et al.
K. Naruke et al., "A New Flash-Erase Eeprom Cell with a Sidewall Select-Gate on its Source Side", reprinted from IEDM Tech. Dig., pp. 603-606 (now 183-185), 1989.
Y. Ma et al., "A Novel High Density Contactless Flash Memory Array Using Split-Gte Source-side-injection Cell for 5V-only Applications", 1994 Symposium of VLSI Technology Digest of Technical Papers, pp. 49-50.

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