Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-05-01
2001-11-06
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000
Reexamination Certificate
active
06312987
ABSTRACT:
This application corresponds to Korean patent application No. 97-17192 filed May 3, 1997 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly to a method for manufacturing having a layer of hemispherical grain polysilicon (referred to herein as “HSG-Si” for use as a capacitor electrode
2. Description of the Related Art
In a dynamic random access memory (DRAM) device, an increase in cell capacitance improves the reading operation of a memory cell and reduces the soft error rate. This greatly improves the operational characteristics of the memory cell. However, as the integration level of semiconductor device increases, the chip area available for each unit memory cell decreases, thereby resulting in a reduction in the area available for each cell capacitor. Therefore, it is necessary to increase the cell capacitance per a unit area to maintain adequate performance at increased integration levels.
Accordingly, much research into methods for increasing the cell capacitance has been conducted. Most of the research has concentrated on modifying the structure of the lower electrodes of cell capacitors. Examples of modified structures that have been proposed are a fin structure, a box structure or a cylindrical structure.
However, increasing the cell capacitance by changing the structure of the lower electrode of the cell capacitors has drawbacks due to a limited design-rule and an increased soft error rate caused by the complicated manufacturing processes required to realize these structures.
Accordingly, a need remains for an improved technique for increasing the capacitance of unit cell capacitors in a semiconductor memory device.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to increase the capacitance of unit cell capacitors in a semiconductor device.
Another object of the present invention is to provide an improved method for manufacturing a semiconductor device having a lower electrode using an HSG-Si layer.
A further object of the present invention is to simplify the fabrication of a semiconductor device having a capacitor that includes an HSG-Si layer.
To accomplish these and other objects, a method for forming a hemispherical grain polysilicon layer on an amorphous silicon film increases the surface area of the layer by first forming silicon crystal nuclei on the film, and then enlarging the nuclei before annealing. The nuclei are formed on the amorphous silicon film loading a substrate having the amorphous silicon film into a chamber and injecting a silicon source gas into the chamber at a first, low flow rate which allows the pressure of the chamber to be reduced, thereby increasing the density of the crystal nuclei. A silicon source gas is then injected into the chamber at a second, higher flow rate, thereby enlarging the silicon crystal nuclei on the amorphous layer. The resulting structure is then annealed to form a hemispherical grain polysilicon layer having a large surface area due to the irregular surface of the polysilicon layer. A dielectric layer is then formed on the polysilicon layer, and an impurity-doped polycrystaline silicon layer is deposited over the dielectric layer to form a capacitor.
One aspect of the present invention is a method for manufacturing a semiconductor device comprising: forming an impurity-doped amorphous silicon layer on a semiconductor substrate; loading the semiconductor substrate into a chamber; injecting a first amount of silicon source gas into the chamber, thereby forming silicon crystal nuclei on the amorphous silicon layer; injecting a second amount of silicon source gas into the chamber, thereby enlarging the silicon crystal nuclei; and annealing the semiconductor substrate, amorphous silicon layer, and silicon crystal nuclei, thereby forming a hemispherical grain polysilicon layer. Injecting a first amount of silicon source gas into the chamber can include injecting silicon source gas into the chamber at a first flow rate, while injecting a second amount of silicon source gas into the chamber includes injecting silicon source gas into the chamber at a second flow rate that is higher than the first flow rate.
Another aspect of the present invention is a method for manufacturing a semiconductor device comprising: loading a semiconductor substrate having an impurity-doped amorphous silicon film into a chamber; heating the semiconductor substrate to a first temperature; injecting a first amount of silicon source gas into the chamber to selectively form first silicon crystal nuclei on the amorphous silicon film; injecting a second amount of silicon source gas into the chamber, thus forming second silicon crystal nuclei larger than the first silicon crystal nuclei; annealing the resultant structure to grow the second silicon crystal nuclei, thus forming a hemispherical grain polysilicon film; and cooling the chamber to a second temperature lower than the first temperature. Injecting a first amount of silicon source gas into the chamber can include injecting silicon source gas into the chamber at a first flow rate, while injecting a second amount of silicon source gas into the chamber includes injecting silicon source gas into the chamber at a second flow rate that is higher than the first rate. The method further includes forming a dielectric layer over the hemispherical grain polysilicon film and forming an electrode layer of the dielectric layer. In a preferred implementation, the first temperature is about 500 to 590 degrees C., and the first amount of silicon source gas is about 60 to 90 percent of the second amount of silicon source gas.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5656531 (1997-08-01), Thakur et al.
patent: 5723379 (1998-03-01), Watanabe et al.
patent: 5960281 (1999-09-01), Nam et al.
Korean App. No. 97-18042, Issued Apr. 30, 1997, Filed Sep. 25, 1995, to Yoon-Ki Kim.
Han Chan-hee
Kang Young-ho
Park Young-kyou
Yang Chang-jip
Samsung Electronics Co,. Ltd.
Tsai Jey
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