Method for manufacturing NOR-type flash memory device

Details Method for manufacturing NOR-type flash memory device Method for manufacturing NOR-type flash memory device

1999-07-13

2001-03-06

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S618000, C438S620000, C438S672000, C438S675000

Reexamination Certificate

active

06197639

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a flash memory device, and more particularly, to a method for fabricating a NOR flash memory device.
2. Description of the Related Art
Among various semiconductor memory devices, a random access memory (RAM) loses data when power is interrupted. A read only memory (ROM), however, retains data even when power is interrupted. Thus, such a ROM is called a non-volatile memory device. A flash memory device is a non-volatile memory device which allows information to be electrically erased or recorded (programmed), and is widely used in computers and memory cards. The flash memory device can be either a NOR flash memory device or a NAND flash memory device. Here, a conventional NOR flash memory device will be described.
FIG. 1
shows the layout of part of a cell array of a conventional NOR flash memory device, and
FIG. 2
is a section view of a unit cell of the NOR flash memory device, taken along line II—II of FIG.
2
.
In the conventional NOR flash memory device of
FIG. 1
, a unit cell is formed in a region where a bit line (B/L) crosses a word line (W/L) at a right angle. The unit cell has a floating gate
7
and a control gate
11
stacked therein. Two unit cells are connected to a bit line (B/L) via a bit line contact region
13
. Also, an active source region
15
parallel with the word line (W/L) is connected to a source line (S/L) parallel with the bit line, via a common source contact region
17
. The active source region
15
is an impurity region formed by implanting impurities into a substrate
1
. Also, as shown in
FIG. 2
, the unit cell of the conventional NOR flash memory device includes the floating gate
7
, a dielectric layer
9
formed on the floating gate
7
, and the control gate
11
formed on the dielectric layer
9
. A tunnel oxide layer
5
is interposed between the floating gate
7
and a semiconductor substrate having a source region
3
a
and a drain region
3
b.
In the above conventional NOR flash memory device, the active source region
15
is connected to the source line (S/L) at intervals of 16 or 32 bits, via the common source contact region
17
. Accordingly, if the cell area is reduced and thus an active width “t” (see
FIG. 1
) of the active source region
15
is reduced, resistance of the active source region
15
increases. Thus, it is impossible to quickly discharge the current of several hundred microamperes (&mgr;A) generated during the operation of the cell.
Also, if all contact regions-the bit line contact region, the source contact region, and the word line contact region of a cell array region, and the active contact region and the gate contact region of a periphery region-are formed by a single photolithography process step, and etching is performed based on the bit line contact region or the source contact region of the cell array region, the active contact region and the gate contact region of the periphery region can be over-etched. Over-etching occurs because the step difference in the cell array region is larger than the step difference in the periphery region.
SUMMARY OF THE INVENTION
To solve above problems, it is an objective of the present invention to provide a method for fabricating a NOR flash memory device, capable of reducing etching damage, which also simplifies a process for forming a contact region of a cell array region and a periphery region.
To achieve the above objective, an improved method for fabricating a NOR flash memory device is provided. The NOR flash memory device has a cell array region including a plurality of unit cells, each having a source and a drain and formed in a region of a silicon substrate where a bit line crosses a word line at right angles, with a bit line contact region exposing each unit cell's drain connected to its bit line, and a word line contact region exposing the word line. Also, the NOR flash memory has a periphery region near the cell array region, including an active contact region exposing the silicon substrate and a gate contact region exposing a gate, wherein the bit line contact region of the cell array region is formed independently, using a different mask, from the word line contact region of the cell array region, and the active contact region and the gate contact region of the periphery region. Preferably, plug ions are implanted into the bit line contact region of the cell array region, and a metal plug is formed in each bit line contact region and word line contact region of the cell array region, and in each active contact region and gate contact region of the periphery region.
Also, there is provided a method for fabricating a NOR flash memory device having a cell array region including a plurality of unit cells, each having a source and a drain and formed in a region of a silicon substrate where a bit line crosses a word line at right angles, with a bit line contact region exposing each unit cell's drain connected to its bit line, and a word line contact region exposing the word line, wherein the bit line contact region of the cell array region is formed independently, using a different mask, from the word line contact region of the cell array region. Preferably, plug ions are implanted into the bit line contact region of the cell array region, and a metal plug is formed in each bit line contact region and the word line contact region of the cell array region.
In the present invention, a word line contact region of a cell array region, and an active contact region and a gate contact region of a periphery region are formed after the fabrication of a bit line contact region of a cell array region. Thus, the contact regions can be stably formed without etching damage.


REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 4933297 (1990-06-01), Lu
patent: 5206187 (1993-04-01), Doan et al.
patent: 5210053 (1993-05-01), Yamagata
patent: 5607873 (1997-03-01), Chen et al.
patent: 5607879 (1997-03-01), Wuu et al.
patent: 5702982 (1997-12-01), Lee et al.
patent: 5766992 (1998-06-01), Chou et al.
patent: 5780336 (1998-07-01), Son
patent: 5877980 (1999-03-01), Mang et al.
patent: 5888887 (1999-03-01), Li et al.
patent: 5926707 (1999-07-01), Seo
patent: 5946548 (1999-08-01), Hashimoto et al.
patent: 6004841 (1999-12-01), Chang et al.

Affiliated with

Also associated with

Rating

Method for manufacturing NOR-type flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing NOR-type flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing NOR-type flash memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2468264