Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-25
2002-04-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S297000
Reexamination Certificate
active
06365457
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 98-10517, filed on Mar. 26, 1998, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method for manufacturing a NOR flash memory device having a stacked gate structure of a floating gate and a control gate.
Semiconductor memory devices are largely divided into Random Access Memories (RAMs), such as Dynamic RAMs (DRAMs) and Static RAMs (SRAMs), and Read Only Memories (ROMs), including Programmable ROMs (PROMs), (Erasable PROMs (EPROMs), and Electrically Erasable PROMs (EEPROMs). RAMs are referred to as volatile memories in that data contained in them is destroyed with the passage of time. In contrast, ROMS are non-volatile memory and retain data once it is entered. Among such ROMs, demands for EEPROMs (Electrically Erasable and Programmable ROMs) are increasing. The EEPROM cells, or the flash memory cells, have a stacked gate structure including a floating gate and a control gate.
Flash memory cells are divided into a NOR type and a NAND type. In the NAND type, which is useful for realizing high integration, unit strings, each containing n cells connected in series, are connected in parallel between bit lines and ground lines. In the NOR type, which allows high-speed operation, individual cells are connected in parallel between bit lines and ground lines.
A description of the structure and operation of a basic NOR flash memory cell, disclosed in IEDM'85, pp. 616~619, “A Single Transistor EPROM Cell And Its Implementation In A 512K CMOS EEPROM”, will be given below with reference to
FIGS. 1
to
3
.
FIG. 1
is a partial layout diagram of a memory cell array in a conventional NOR flash memory device,
FIG. 2
is an equivalent circuit diagram of the memory cell array of
FIG. 1
, and
FIG. 3
is a cross-sectional view of a unit cell. Reference numeral
10
denotes a semiconductor substrate; reference numeral
11
denotes an active source region; reference no numeral
14
denotes a tunnel oxide film; reference numeral
16
denotes a floating gate; reference numeral
18
denotes an interpoly dielectric layer; reference numeral
20
denotes a control gate, reference numerals
24
a
and
24
b
denote source and drain regions, respectively; and reference numeral
28
denotes a bit line contact.
Referring to
FIGS. 1
to
3
, a memory cell array has a plurality of bit lines B/L arranged at specified intervals, a plurality of word lines W/L and a plurality of source lines CSL. A unit cell in the array contains a stacked gate structure including the floating gate
16
and the control gate
20
. Each unit cell is formed in an area where the word line W/L perpendicularly intersects one of the metal bit lines B/L. Two individual cells are connected to the bit line B/L by a single bit line contact
28
, and the active source region
11
formed of an impurity layer and disposed in parallel with the word line W/L, is connected by the source line CSL arranged in parallel with the bit line B/L for tens of bits.
In a unit cell, the he tunnel oxide film
14
is interposed between the floating gate
16
and the substrate
10
, and the interpoly dielectric layer
18
is interposed between the floating gate
16
and the control gate
20
. The source and drain regions
24
a
and
24
b
are formed in the surface of the substrate
10
in self-alignment with the stacked gate. The floating gate
16
extends across an active region and portions of the edges of field regions at both sides of the active region, thus being isolated from that of an adjacent cell. The control gate
20
is connected to that of an adjacent cell, thus forming a word line W/L.
Adjacent cells are formed in opposite directions, sharing the source/drain regions
24
a
and
24
b
. The drain region
24
b
of a unit cell is connected to that of an adjacent cell in the same row, and has the bit line contact
28
formed therein. Bit line contacts
28
in the same row are electrically connected by the bit line B/L perpendicular to the word line W/L. That is, two cells are connected to the bit line B/L by a single bit line contact
28
.
The source region
24
a
of the unit cell is connected to that of an adjacent cell in the same column through the active source region
11
formed of an impurity diffusion layer parallel to the word line W/L. In addition, to reduce the resistance of the source line, a single source line contact is formed in the active source region
11
parallel to the word line W/L, for a plurality of bit lines B/L. The source line CSL parallel to the bit line B/L is electrically connected to the active source region
11
through the source line contact
29
.
Such a general NOR flash memory cell is programmed by CHE (channel hot electron) injection and erased through a source or a bulk substrate by Fowler-Nordheim tunneling (F-N tunneling).
For a programming operation, the threshold voltage V
th
of a cell is increased from an initial level of about 2V, to about 7V by storing electrons on the floating gate
16
. In other words, by applying 6~7V to the selected bit line B/L, 10~12V to the selected word line W/L, and 0V to the source and the bulk substrate, parts of the CHEs are introduced onto the floating gate
16
via the tunnel oxide film
18
by a gate electric field. In this way, the cell is programmed.
For an erasing operation, the threshold voltage V
th
of the cell is dropped to the initial level, i.e., about 2V, by removing electrons from the floating gate
16
. In other words, by floating the selected bit line B/L and applying 12~15V to the source and 0V to the selected word line W/L, the electrons are removed from the floating gate
16
to the source junction via the tunnel oxide film
18
of about 100 Å by Fowler-Nordheim tunneling, due to a potential difference between the floating gate
16
and the source junction. Typically, since the source junctions of all cells are electrically connected to one by the active source region
11
, cells are collectively erased in block units each block being hundreds to thousands of bits. Furthers since the source voltage during the erasing operation is higher than the drain voltage during the programming operation, the source junction is formed to be a double diffused junction (hereinafter referred to as a “DD”) structure as shown in
FIG. 3
so as to make the source junction have higher breakdown voltage than the drain junction.
A reading operation determines the presence or absence of a current path through erased and programmed cells by applying about 1V to the selected bit line B/L and 4~5V to the word line W/L.
The source line CSL serves to discharge to a ground node the great amounts of current generated by the cells during programming and reading operations. To discharge large amount of current in a short time in the flash memory cell using CHE injection, one source line CSL is formed for every 16~32 bits.
During the programming and erasing operations, the F-N tunneling characteristics or the hot electron generation efficiency may be varied according to the dimension of the cell. In particular if the cell size is reduced, as it is with highly integrated devices, the loss of efficiency can become serious. For example, in the case of a cell having a short channel length, the punching characteristics between the source and the drain become degraded, while the hot electron generation efficiency is increased by the increase of cell current during a programming operation, thus allowing short programming time. Furthermore, when the overlap area between the source junction and the floating gate is increased during the source erasing operation, the voltage V
f
induced at the floating gate when a source voltage V
s
is applied is given by
V
f
=(C
s
/C
t
)V
s
(1)
where C
s
is an overlap capacitance between the source junction and the floating gate and C
t
is a total capacitance, i.e
Estrada Michelle
Fourson George
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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